User's Manual

PRELIMINARY
CYBLE-224110-00
Document Number: 002-11264 Rev. *A Page 21 of 43
C
LOAD
Stable up to maximum load. Performance
specs at 50 pF
––125 pF –
Slew_rate
Cload = 50 pF, Power = High,
V
DDA
≥ 2.7V
6– –V/µsec –
T_op_wake
From disable to enable, no external RC
dominating
– 300 – µsec –
Comp_mode (Comparator Mode; 50-mV Drive, T
RISE
= T
FALL
(Approx.)
T
PD1
Response time; power = high – 150 – nsec –
T
PD2
Response time; power = medium – 400 – nsec –
T
PD3
Response time; power = low – 2000 – nsec –
Vhyst_op Hysteresis – 10 – mV –
Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for V
DDA
> 2.5V)
GBW_DS Gain bandwidth product – 50 – kHz –
IDD_DS Current – 15 – µA –
Vos_DS Offset voltage – 5 – mV –
Vos_dr_DS Offset voltage drift – 20 – µV/°C –
Vout_DS Output voltage 0.2 – V
DD
–0.2 V –
Vcm_DS Common mode voltage 0.2 – V
DD
–1.8 V –
Table 18. Opamp Specifications (continued)
Parameter Description Min Typ Max Unit Details/Conditions
Table 19. Comparator DC Specifications
Parameter Description Min Typ Max Unit Details/Conditions
V
OFFSET1
Input offset voltage, Factory trim – – ±10 mV –
V
OFFSET2
Input offset voltage, Custom trim – – ±6 mV –
V
OFFSET3
Input offset voltage, ultra-low-power mode – ±12 – mV –
V
HYST
Hysteresis when enabled – 10 35 mV –
V
ICM1
Input common mode voltage in normal mode 0 – V
DDD
–0.1 V Modes 1 and 2
V
ICM2
Input common mode voltage in low-power
mode
0– V
DDD
V–
V
ICM3
Input common mode voltage in ultra
low-power mode
0–V
DDD
–1.15 V –
CMRR Common mode rejection ratio 50 – – dB V
DDD
≥ 2.7V
CMRR Common mode rejection ratio 42 – – dB V
DDD
≤ 2.7V
I
CMP1
Block current, normal mode – – 400 µA –
I
CMP2
Block current, low-power mode – – 100 µA –
I
CMP3
Block current in ultra-low-power mode – 6 – µA –
Z
CMP
DC input impedance of comparator 35 – – MΩ –