Datasheet

Aalap Tripathy, 2004P3PS208
PSOC Lab, BITS Pilani Goa Campus
31
• Filters Æ BPF2_1 & BPF2_2
• Counters Æ Counter16_1
• Counters Æ Counter8_1 & Counter8_2
• Amplifiers Æ PGA_1
12. Switch from the user module view to
the Interconnect view
Use standard procedure to place all blocks in the design. The following is a quick revision of the steps
13. Click on the clock input of the 16 bit counter. Select VC1 as shown. This makes it get a clock signal of SysClk=24 Mhz.
You can use VC3 to do this if you only need 8 bit divider. This will keep the digital block free for other things.