Specifications

ManualsBrandsCypress Semiconductor ManualsComputer equipmentCY14B256K

CY14B256K

256 Kbit (32K x 8) nvSRAM

with Real Time Clock

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06431 Rev. *G Revised May 05, 2008

Features

■ Data integrity of Cypress nvSRAM combined with full featured

real time clock

❐ Low power, 300 nA Max, RTC current

❐ Capacitor or battery backup for RTC

■ Watchdog timer

■ Clock alarm with programmable interrupts

■ 25 ns, 35 ns, and 45 ns access times

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap™ initiated by software, device pin, or

on power down

■ RECALL to SRAM initiated by software or on power up

■ Infinite READ, WRITE, and RECALL cycles

■ High reliability

❐ Endurance to 200K cycles

❐ Data retention: 20 years at 55°C

■ 10 mA typical I

at 200 ns cycle time

■ Single 3V operation with tolerance of +20%, -10%

■ Commercial and industrial temperature

■ SSOP package (ROHS compliant)

Functional Description

The Cypress CY14B256K combines a 256 Kbit nonvolatile static

RAM with a full-featured real time clock in a monolithic integrated

circuit. The embedded nonvolatile elements incorporate

QuantumTrap technology producing the world’s most reliable

nonvolatile memory. The SRAM is read and written an infinite

number of times, while independent, nonvolatile data resides in

the nonvolatile elements.

The real time clock function provides an accurate clock with leap

year tracking and a programmable high accuracy oscillator. The

alarm function is programmable for one time alarms or periodic

seconds, minutes, hours, or days. There is also a programmable

watchdog timer for process control.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

512 X 512

QuantumTrap

512 X 512

STORE

RECALL

COLUMN IO

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

RTC

MUX

INT

RTCbat

RTCcap

Logic Block Diagram

[+] Feedback

Summary of content (24 pages)

PAGE 1
CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock Features Functional Description ■ Data integrity of Cypress nvSRAM combined with full featured real time clock ❐ Low power, 300 nA Max, RTC current ❐ Capacitor or battery backup for RTC ■ Watchdog timer ■ Clock alarm with programmable interrupts The Cypress CY14B256K combines a 256 Kbit nonvolatile static RAM with a full-featured real time clock in a monolithic integrated circuit.
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CY14B256K Pin Configurations V CAP 1 48 V CC NC A 14 2 47 NC 3 46 HSB 4 45 5 44 WE A 13 A 12 A7 A6 6 43 A5 7 42 A9 INT 8 41 NC A4 9 NC 10 NC 11 NC V SS 12 NC 14 13 A8 48-SSOP 40 A 11 39 NC 38 NC Top View 37 NC 36 (Not To Scale) V SS 35 NC V RTCcap V RTCbat 15 34 DQ0 16 33 DQ 6 A3 17 32 A2 18 31 OE A 10 A1 19 30 A0 CE 20 29 DQ7 DQ5 DQ1 21 28 DQ2 22 27 DQ4 X1 23 26 DQ3 X2 24 25 V CC Pin Definitions Pin Name IO Type A
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CY14B256K SRAM Read Figure 1. AutoStore Mode V CC V CC 0.1UF V CAP 10k Ohm The CY14B256K nvSRAM consists of two functional components paired in the same physical cell. The components are SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM transfers to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This architecture enables all cells to store and recall in parallel.
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CY14B256K During any STORE operation, regardless of how it is initiated, the CY14B256K continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the CY14B256K remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. Hardware RECALL (Power Up) During power up or after any low power condition (VCC is less than VSWITCH), an internal RECALL request is latched.
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CY14B256K Table 1.
PAGE 6
CY14B256K Clock Operations The Clock registers maintain time up to 9,999 years in one second increments. The user sets the time to any calendar time and the clock automatically keeps track of days of the week, month, leap years, and century transitions. There are eight registers dedicated to the clock functions that are used to set time with a write cycle and to read time during a read cycle. These registers contain the time of day in BCD format.
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CY14B256K To determine how to set the calibration, one may set the CAL bit in the Flags register at 0x7FF0 to ‘1’ that causes the INT pin to toggle at a nominal 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.010124 Hz indicates a +20 ppm error, requiring to load a –10 (001010) into the Calibration register. Note that setting or changing the Calibration register does not affect the frequency test output frequency.
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CY14B256K Interrupts The CY14B256K provides three potential interrupt sources. They include the watchdog timer, the power monitor, and the clock or calendar alarm. Each is individually enabled and assigned to drive the INT pin. In addition, each has an associated flag bit that the host processor uses to determine the cause of the interrupt. Some of the sources have additional control bits that determine functional behavior.
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CY14B256K . Figure 4. RTC Recommended Component Configuration WDF Watchdog Timer WIE PF Power Monitor PFE P/L VCC Pin Driver INT VINT H/L AF Clock Alarm VSS WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low AIE Recommended Values Y1 = 32.768 KHz RF = 10M Ohm C1 = 0 C2 = 56 pF Document Number: 001-06431 Rev.
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CY14B256K Table 3.
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CY14B256K Table 4. Register Map Detail (continued) Time Keeping - Hours 0x7FFB D7 D6 12/24 0 D5 D4 D3 D2 10s Hours D1 D0 Hours Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23. Time Keeping - Minutes D7 0x7FFA D6 0 D5 D4 D3 D2 10s Minutes D1 D0 Minutes Contains the BCD value of minutes.
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CY14B256K Table 4. Register Map Detail (continued) Interrupt Status/Control 0x7FF6 D7 D6 D5 D4 D3 D2 D1 D0 WIE AIE PFIE 0 H/L P/L 0 0 WIE Watchdog Interrupt Enable. When set to ‘1’ and a watchdog time out occurs, the watchdog timer drives the INT pin and the WDF flag. When set to ‘0’, the watchdog time out affects only the WDF flag. AIE Alarm Interrupt Enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the alarm match only affects the AF flag.
PAGE 13
CY14B256K Table 4. Register Map Detail (continued) Flags 0x7FF0 D7 D6 D5 D4 D3 D2 D1 D0 WDF AF PF OSCF 0 CAL W R WDF Watchdog Timer Flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach ‘0’ without being reset by the user. It is cleared to ‘0’ when the Flags or Control register is read. AF Alarm Flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers with the match bits = 0.
PAGE 14
CY14B256K Maximum Ratings Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260°C Storage Temperature ................................. –65°C to +150°C Output Short Circuit Current [6] ....................................
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CY14B256K Capacitance These parameters are guaranteed but not tested. Parameter Description Max Unit 7 pF 7 pF Test Conditions 48-SSOP Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA / JESD51. TBD °C/W TBD °C/W CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V Thermal Resistance These parameters are guaranteed but not tested.
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CY14B256K AC Switching Characteristics Parameter Cypress Alt.
PAGE 17
CY14B256K AutoStore or Power Up RECALL Parameter tHRECALL [15] [16, 17] CY14B256K Description Min Unit Max Power Up RECALL Duration 20 ms STORE Cycle Duration 12.5 ms VSWITCH Low Voltage Trigger Level 2.
PAGE 18
CY14B256K RTC Characteristics Parameter IBAK [23] VRTCbat VRTCcap Description Test Conditions Min RTC Backup Current [24] [25] tOCS RTC Battery Pin Voltage RTC Capacitor Pin Voltage RTC Oscillator Time to Start Max Unit Commercial 300 nA Industrial 350 nA Commercial 1.8 3.3 V Industrial 1.8 3.3 V Commercial 1.2 2.7 V Industrial 1.2 2.
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CY14B256K Switching Waveforms (continued) Figure 7. SRAM Write Cycle 1: WE Controlled [26, 27] tWC ADDRESS tHA tSCE CE tAW tSA tPWE WE tSD tHD DATA VALID DATA IN tHZWE DATA OUT tLZWE HIGH IMPEDANCE PREVIOUS DATA Figure 8. SRAM Write Cycle 2: CE Controlled tWC ADDRESS CE WE tHA tSCE tSA tAW tPWE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Note 27. CE or WE are greater than VIH during address transitions. Document Number: 001-06431 Rev.
PAGE 20
CY14B256K Switching Waveforms (continued) Figure 9. AutoStore/Power Up RECALL No STORE occurs without atleast one SRAM write STORE occurs only if a SRAM write has happened VCC VSWITCH tVCCRISE AutoStore tSTORE tSTORE POWER-UP RECALL tHRECALL tHRECALL Read & Write Inhibited Figure 10. CE Controlled Software STORE/RECALL Cycle [19] tRC tSCE ADDRESS # 6 ttGHAX GLAX OE a a a a a a a a tSA CE a a a a ADDRESS # 1 ADDRESS tRC DQ (DATA) DATA VALID Document Number: 001-06431 Rev.
PAGE 21
CY14B256K Switching Waveforms (continued) Figure 11. OE Controlled Software STORE/RECALL Cycle [19] tRC ADDRESS # 1 ADDRESS CE tSA ADDRESS # 6 tSCE OE t STORE / t RECALL DQ (DATA) a a ttGHAX GLAX DATA VALID a a a a a a a a a a a a tRC HIGH IMPEDANCE DATA VALID Figure 12. Soft Sequence Processing [20, 21] ADDRESS # 1 ADDRESS # 6 34 t SS Soft Sequence Command ADDRESS # 1 a a ADDRESS a a Soft Sequence Command 34 t SS ADDRESS # 6 VCC Figure 13.
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CY14B256K Part Numbering Nomenclature CY 14 B 256 K - SP 25 X C T Option: T-Tape and Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Pb-Free Package: SP - 48-SSOP Voltage: B - 3.0V Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Data Bus: K - x8 + RTC Density: 256 - 256 Kb nvSRAM 14 - AutoStore + Software Store + Hardware Store Cypress Document Number: 001-06431 Rev.
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CY14B256K Ordering Information All the below mentioned parts are Pb-free. Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts.
PAGE 24
CY14B256K Document History Page Document Title: CY14B256K, 256 Kbit (32K x 8) nvSRAM with Real Time Clock Document Number: 001-06431 REV. ECN NO. Issue Date Orig. of Change ** 425138 See ECN TUP New data sheet *A 437321 See ECN TUP Show data sheet on external Web *B 471966 See ECN TUP Changed VIH(min) from 2.2V to 2.