Datasheet

CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Document Number: 001-85330 Rev. *G Page 22 of 37
I
2
C Specifications
Figure 15. I
2
C Bus Timing Diagram for Fast or Standard Modes
Table 16. I
2
C Specifications
Parameter Description Conditions Min Typ Max Units
FSCLI2C_FM
I
2
C SCL clock frequency
0 – 400 kHz
THDSTAI2C_FM
Hold time (repeated) START condition; after this
period, the first clock pulse is generated
0.6 – – µs
TSUSTAI2C_FM
Setup time for a repeated START condition 0.6 – – µs
TLOWI2C_FM
LOW period of the SCL clock 1.3 – – µs
THIGHI2C_FM
HIGH period of the SCL clock 0.6 – – µs
THDDATI2C
Data hold time 0 – –µs
TSUDATI2C_FM
Data setup time 100 – – ns
TSUSTOI2C_FM
Setup time for I
2
C STOP condition
0.6 – – µs
CB_FM
Capacitive load for each I
2
C bus line
– – 400 pF
TVDDATI2C_FM
Data valid time – – 0.9 µs
TVDACKI2C_FM
Data valid acknowledge time – – 0.9 µs
TSPI2C_FM
Pulse width of spikes suppressed by the input filter – – 50 ns
TBUFI2C_FM
Bus-free time between STOP and START condition 1.3 – – µs
VIL_I2C
Input LOW voltage 2-mA sink –0.5 –
0.3 * V
DD
V
VIH_I2C
Input HIGH Voltage 3-mA sink
0.7* V
DD
– –V
VOL_I2C_L
Output LOW voltage, low supply range
V
DD
< 2 V, 3-mA sink
– –
0.2 * V
DD
V
VOL_I2C_H
Output LOW voltage, high supply range
V
DD
> 2 V, 3-mA sink
– – 0.4 V
IOL_I2C_FM
I
2
C output low current
Fast Mode, 1.71 V ≤ V
DD
≤
5.5 V, load = CB_SM, V
OL
=
0.6 V
6 – –mA
I2C_VHYS_HV
I
2
C input hysteresis
Fast and standard mode I2C
speeds. 2 V ≤ V
DD
≤ 4.5 V
0.05 * V
DD
– –mV
I2C_VHYS_5V5
I
2
C input hysteresis
Fast and standard mode I2C
speeds. 4.5 V < V
DD
< 5.5 V
200 – – mV
I2C_VHYS_LV
I
2
C input hysteresis
Fast and standard mode I2C
speeds. V
DD
< 2 V
0.1 * V
DD
– –mV
SDA
SCL
S
T
HDSTAI2C
T
LOWI2C
T
HIGHI2C
T
SUSTAI2C
T
HDDATI2C
T
SUDATI2C
P
T
SUSTOI2C
S
T
BUFI2C