Datasheet
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Document Number: 001-85330 Rev. *G Page 28 of 37
I
2
C Communication Guidelines
1. After device reset, the host should wait for T
I2CBOOT
time
before initiating any I
2
C communication. The CY8CMBR3xxx
CapSense controller family will generate a NACK if the host
tries to communicate before this period.
2. The CY8CMBR3xxx controller is expected to NACK the
address match event if it is in the standby mode (during any
of the operational states – Deep Sleep, Look-for-Touch,
Look-for-Proximity, or Active). The controller wakes up from
the standby mode on an address match but sends NACK until
it transitions into the Active state. When the device NACKs a
transaction the host is expected to retry the transaction until
it receives an ACK.
3. If there is a delay of more than 340 ms between two subse-
quent bytes within an I
2
C transaction, the device may go into
standby mode and the host may get a NACK.
4. When the host sends the SAVE_CHECK_CRC command, the
device will send a NACK on any subsequent I
2
C transactions
until the command execution is completed. The time taken to
complete the SAVE_CHECK_CRC command is 220 ms typ.
5. The host must not write to read-only registers. All write opera-
tions directed to such read-only registers are ignored.
Write Operation
A host performs the following steps during a write operation:
1. The host sends the START condition.
2. The host specifies the slave address, followed by the
read/write bit to specify a write operation.
3. The device may NACK the host.
4. The host sends a Repeat Start (or a stop followed by a start
condition), followed by the address and read/write bit, to
specify a write operation. The host keeps sending the Repeat
Start with the address and read/write bits until the device
sends an ACK. The device ACKs the host.
5. The host specifies the register address to which it has to write.
6. The device ACKs the host.
7. The host starts sending the data to the device, which is written
to the register address specified by the host. This is followed
by an ACK from the device.
8. If the write operation includes more bytes, each one is written
to the successive register address. Each successive byte is
followed by an ACK from the device.
9. After the write operation is complete, the host sends the STOP
condition to the device. This marks the end of the communi-
cation (see Figure 18).
Figure 18. Host Writing x Bytes to the Device
Setting the Device Data Pointer
The host sets the device data pointer to specify the starting point
for future read operations. Setting the device data pointer
involves the following steps:
1. The host sends the START condition.
2. The host specifies the slave address, followed by the
read/write bit to specify a write operation.
3. The device may NACK the host.
4. The host sends a Repeat Start, followed by the address and
read/write bit, to specify a write operation. The host keeps
sending the repeat start with the address and read/write bit
until the device sends an ACK.
5. The device ACKs the host.
6. The host specifies the register address. Any further read
operation will take place from this address.
7. The host sends the STOP condition (see Figure 19).
Figure 19. Host Setting the Device Data Pointer
Slave
Address
`
Register
Address(n)
Data[n] Data[n+1] Data[n+x]
S
A
6
A
5
A
4
A
3
A
2
A
1
A
0
R
W
A
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
A
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A P
ACK
ACK
ACK
ACK
ACK
Write
Start
Stop
N
Start
NACK
S
A
6
A
5
A
4
A
3
A
2
A
1
A
0
R
W
N
Slave
Address
`
Start
NACK
S
A
6
A
5
A
4
A
3
A
2
A
1
A
0
R
W
AAP
Slave
Address
`
ACK
ACK
Write
Start
Stop
R
5
R
4
R
3
R
2
R
1
R
7
R
6
R
0
N
Start
NACK
Register
pointer
S
A
6
A
5
A
4
A
3
A
2
A
1
A
0
R
W
N
Slave
Address
`
Start
NACK