Datasheet
CY7C1307BV25
CY7C1305BV25
Document Number: 38-05630 Rev. *B Page 21 of 21
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the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
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Document History Page
Quad Data Rate SRAM and QDRSRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and
Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document Title: CY7C1305BV25/CY7C1307BV25 18-Mbit Burst of Four Pipelined SRAM with QDR™ Architecture
Document Number: 38-05630
REV. ECN NO.
Submission
Date
Orig. of
Change Description of Change
** 253049 See ECN SYT New Data Sheet
*A 436864 See ECN NXR Converted from Preliminary to Final.
Removed 133 MHz & 100 MHz from product offering.
Included industrial Operating Range.
Changed C/C
Description in the Features Section & Pin Description Table.
Changed t
TCYC
from 100 ns to 50 ns, changed t
TF
from 10 MHz to 20 MHz
and changed t
TH
and t
TL
from 40 ns to 20 ns in TAP AC Switching
Characteristics table
Modified the ZQ pin definition as follows:
Alternately, this pin can be connected directly to V
DDQ
, which enables the
minimum impedance mode
Included Maximum Ratings for Supply Voltage on V
DDQ
Relative to GND
Changed the Maximum Ratings for DC Input Voltage from V
DDQ
to V
DD.
Modified the Description of I
X
from Input Load current to Input Leakage
Current on page # 16.
Modified test condition in note# 16 from V
DDQ
< V
DD
to
V
DDQ
V
DD
Updated the Ordering Information table and replaced the Package Name
Column with Package Diagram.
*B 2896654 03/20/2010 NJY Removed inactive parts from Ordering Information table; Updated package
diagram.
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