X5-GSPS User's Manual
X5-GSPS User's Manual The X5-GSPS User's Manual was prepared by the technical staff of Innovative Integration on February 5, 2009. For further assistance contact: Innovative Integration 2390-A Ward Ave Simi Valley, California 93065 PH: FAX: (805) 578-4260 (805) 578-4225 email: techsprt@innovative-dsp.com Website: www.innovative-dsp.com This document is copyright 2009 by Innovative Integration. All rights are reserved. VSS \ Distributions \ X5-GSPS \ Documentation \ Manual \ X5GSPSMaster.
Table of Contents X5-GSPS User's Manual...........................................................................................................................2 List of Tables.............................................................................................................................7 List of Figures...........................................................................................................................8 Chapter 1:Introduction.............................................
System Requirements..............................................................................................................................26 Power Considerations..............................................................................................................................26 Mechanical Considerations.....................................................................................................................27 Chapter 5:About the X5 XMC Modules....................................
Stream Initialization.........................................................................................................................60 Data Required Event Handler...........................................................................................................62 The Wave Example for Linux.................................................................................................................64 The ApplicationIo Class.................................................................
Where to start?....................................................................................................................................87 Getting Good Analog Performance...................................................................................................88 Performance Data....................................................................................................................................88 Power Consumption.............................................................
List of Tables Table 1. X5 XMC Bus Requirements....................................................................................................23 Table 2. Required PCIe Resource Allocations......................................................................................26 Table 3. XMC Mounting Hardware......................................................................................................27 Table 4. X5 XMC Family.........................................................................
List of Figures Figure 1. Innovative Install Program...................................................................................................15 Figure 2. Progress is shown for each section........................................................................................16 Figure 3. ToolSet registration form.......................................................................................................17 Figure 4. BusMaster configuration.................................................
Chapter 1: Introduction Real Time Solutions! Thank you for choosing Innovative Integration, we appreciate your business! Since 1988, Innovative Integration has grown to become one of the world's leading suppliers of DSP and data acquisition solutions. Innovative offers a product portfolio unrivaled in its depth and its range of performance and I/O capabilities .
Introduction What is X5-GSPS? The X5- GSPS is a PCI Express XMC IO module featuring a National ADC08D1500, 1.6 GSPS, 8-bit A/D dual-channel A/ D converter. A Xilinx Virtex5 SX95T with 512 MByte DDR2 DRAM and 4MB QDR-II memory provide a very high performance DSP core for demanding applications such as emerging wireless standards. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates exceeding 300 GMACs per second.
Introduction What is wxWidgets? wxWidgets was started in 1992 by Julian Smart at the University of Edinburgh. Initially started as a project for creating applications portable across Unix and Windows, it has grown to support the Mac platform, WinCE, and many other toolkits and platforms. The number of developers contributing to the project is now in the dozens and the toolkit has a strong userbase that includes everyone from open source developers to corporations such as AOL.
Introduction Finding detailed information on Malibu Information on Malibu is available in a variety of forms: • Data Sheet (http://www.innovative-dsp.com/products/malibu.htm) • On-line Help • Innovative Integration Technical Support • Innovative Integration Web Site (www.innovative-dsp.com) Online Help Help for Malibu is provided in a single file, Malibu.chm which is installed in the Innovative\Documentation folder during the default installation.
Introduction Typeface Source Listing Boldface Emphasis Cpp Variable Cpp Symbol KEYCAPS Menu Command X5-GSPS User's Manual Meaning Text in this style represents text as it appears onscreen or in code. It also represents anything you must type. Text in this style is used to strongly emphasize certain words. Text in this style is used to emphasize certain words, such as new terms.
Windows Installation Chapter 2: Windows Installation This chapter describes the software and hardware installation procedure for the Windows platform (WindowsXP and Vista). Do NOT install the hardware card into your system at this time. This will follow the software installation. Host Hardware Requirements The software development tools require an IBM or 100% compatible Pentium IV - class or higher machine for proper operation.
Windows Installation Starting the Installation To begin the installation, start Windows. Shut down all running programs and disable anti-virus software. Insert the installation DVD. If Autostart is enabled on your system, the install program will launch. If the DVD does not Autostart, click on Start | Run... Enter the path to the Setup.bat program located at the root of your DVD-ROM drive (i.e. E:\Setup.bat) and click “OK” to launch the setup program. SETUP.
Windows Installation Figure 2. Innovative Install Program Using this interface, specify which product to install, and where on your system to install it. 1) Select the appropriate product from the Product Menu. 2) Specify the path where the development package files are to be installed. You may type a path or click “Change” to browse for, or create, a directory. If left unchanged, the install will use the default location of “C:\Innovative”.
Windows Installation Figure 3. Progress is shown for each section. Tools Registration At the end of the installation process you will be prompted to register. If you decide that you would like to register at a later time, click “Register Later”.
Windows Installation When you are ready to register, click Start | All Programs | Innovative | | Applets. Open the New User folder and launch NewUser.exe to start the registration application. The registration form to the left will be displayed. Before beginning DSP and Host software development, you must register your installation with Innovative Integration. Technical support will not be provided until registration is successfully completed.
Windows Installation Figure 6. Installation complete Click the “Shutdown Now” button to shut down your computer. Once the shutdown process is complete unplug the system power cord from the power outlet and proceed to the next section, “Hardware Installation.” Hardware Installation Now that the software components of the Development Package have been installed the next step is to configure and install your hardware.
Windows Installation X5-GSPS User's Manual 20
Installation on Linux Chapter 3: Installation on Linux This chapter contains instruction on the installation of the baseboard software for Linux operating systems. Software installation on Linux is performed by loading a number of packages. A Package is a special kind of archive file that contains not only the files that are to be installed, but also installation scripts and dependency information to allow a smooth fit into the system. This information allows the package to be removed, or patched.
Installation on Linux The installation CD, or the web site contains a file called LinuxNotes.pdf giving instructions on how to load these packages and how to install the drivers onto your Linux machine. This file is also loaded onto the target machine by the the MalibuLinuxRed RPM. These procedures need to be completed for every target machine. Malibu To develop software for a baseboard the Malibu packages also must be installed. Malibu Packages Description Malibu-LinuxPeriphLib-[ver]-[rel].i586.
Installation on Linux Board Packages Baseboard Packages Description X5-400M Malibu-LinuxPeriphLib-[ver]-[rel].i586.rpm Board files and examples. X5-210M X5-210M-LinuxPeriphLib-[ver]-[rel].i586.rpm Board files and examples. X3-10M X3-10M-LinuxPeriphLib-[ver]-[rel].i586.rpm Board files and examples. X3-25M X3-25M-LinuxPeriphLib-[ver]-[rel].i586.rpm Board files and examples. X3-A4D4 X3-A4D4-LinuxPeriphLib-[ver]-[rel].i586.rpm Board files and examples. X3-SD X3-SD-LinuxPeriphLib-[ver]-[rel].
Installation on Linux Completing the Board Install The normal board install is complete with the installation of the files. The board driver install is already complete with the loading of the Malibu Red package. If there are any board-specific steps they will be listed at the end of this chapter. Linux Directory Structure When a board package is installed, its files are placed under the /usr/Innovative folder.
Hardware Installation Chapter 4: Hardware Installation The X5 XMC cards may be used on a variety of host cards supporting an XMC.3 PCI Express (VITA standard 42.3 compatible) site. XMC P16 is also used for system integration including use as a dedicated data channel. Compatible Host Cards X5 XMC cards are compatible with the VITA 42.3 PCI Express mezzanine module sites. The card form factor is IEEE 1386 with XMC connectors P15 and P16.
Hardware Installation Figure 7. Innovative Single lane PCIe – XMC.3 adapter card (P/N 80172) Figure 8. Innovative PCI 64/66 – XMC.3 (4x lanes) adapter card (P/N 80167-0) Figure 9. Innovative x8 Lane PCI Express – XMC.
Hardware Installation Figure 10. eInstrument Node – cabled PCI Express adapter (x1 lane) for XMC Modules (II P/N 90181) Figure 11. eInstrument PC – embedded PC (Windows/Linux) hosts two XMC modules (II P/N 90199) XMC systems should be be compatible with VITA 42.3 specification for P15. The P16 interface can only be used when the PCI Express interface is present and active. The XMC P16 interface to the host may be customized in the Application Logic.
Hardware Installation Table 2. Required PCIe Resource Allocations Required PCIe Resources BAR0 : 1MB Memory BAR1 : 64K B Memory 1 Interrupt When you first plug in the module, it will then be found and the driver should be installed for the module. The standard driver resides in the \Innovative\drivers directory after software installation. The XMC module may be used an any PCI Express slot supporting 1 or more lanes.
Hardware Installation Mechanical Considerations The X5 modules conform to IEEE1386 CMC specification and ANSI/VITA 42.0 specifications. These specifications define the size of the module and mounting requirements. In short the modules are 75 x 150 mm and mount 10 mm from the host card. This allows the XMC modules to fit in one slot in desktop PC or compact PCI systems. For ruggedness, the modules should be mounted to a host card using the mounting screws and standoffs.
About the X5 XMC Modules Chapter 5: About the X5 XMC Modules In this chapter, we will discuss the common features of the X5 module family. Specifics on each module are covered in later chapters. X5 XMC Architecture The X5 XMC modules share a common architecture and many features such as the PCI Express interface, data buffering features, the Application Logic, and other system integration features.
About the X5 XMC Modules X5 XMC Features Applications 500M updates/sec X5-210M 4 A/D channels, 14 bit, 250 MHz Software radio, RADAR X5-GSPS 2 A/D channels at 1.5GSPS IF/RF simulation and test, RADAR X5-COM 4 SFP ports at 3.125 Gbps Remote IO, system expansion The X5 XMCs feature a Xilinx Virtex-5 SX95T core for signal processing and control.
About the X5 XMC Modules Table 6. X5 Computing Core Devices Feature Device Part Number Application Logic FPGA Xilinx Virtex-5 SX95T XC5VSX95T-1FFG1136C Computation memory QDR2 SRAM 2x Cypress CY7C1314BV18-167 Buffer memory DDR2 DRAM 4x Micron MT47H64M16HR-37E As the focus of the module, the X5 computing core connects the IO, peripherals, host communications and support features.
About the X5 XMC Modules Table 7. PCI Express Standards Compliance Standard Describes Standards Group PCI Express 1.0a PCI Express electrical and protocol standards. 2.5 Gbps data rate per lane per direction. PCI SIG ( http://www.picmg.com ) ANSI/VITA 42 XMC module mechanicals and connectors VITA ( www.vita.org ) ANSI VITA 42.3 XMC module with PCI Express Interface. VITA ( www.vita.org ) The major interfaces to the application logic are the data link, command channel and SelectMAP interface.
About the X5 XMC Modules The SRAM devices connected to the FPGA are 4 Mbytes total size, organized as two banks of 16Mbitx32 dual ported memory. This device is an Cypress CY7C1314 (or equivalent) which is a synchronous QDR2 SRAM and supports clock rates up to 167 MHz. All SRAM control and data lines pins are directly connected to the FPGA, allowing the SRAM memory control to be customized to the application.
About the X5 XMC Modules Use the baseboard IdRom() method to obtain a reference to the internally-managed IUsesPmcEeprom object, as shown below: // Open the module Innovative::X5_400M Module; Module.Target(0); Module.Open(); // Create a 50-32-bit-word section at offset zero in ROM user space PmcIdromSection Section1(Module.IdRom().Rom(), PmcIdrom::waUser, 0, 50); // Create a 50-32-bit-word section at offset 50 in ROM user space PmcIdromSection Section2(Module.IdRom().
About the X5 XMC Modules Function Type DioPortData() Description Property Broadside Read/Write to low-order 32-bits of DIO. Typical use of the digital IO port involves first configuring the port using the Config() operator. This sets the byte direction and the clock mode. The port is then ready for read/write configurations to each port. For instance: // Open the module Innovative::X5_400M Module; Module.Target(0); Module.Open(); // All bits input Module.
About the X5 XMC Modules Data may be written to/read from the digital I/O port using the digital I/O port data registers. Data written to ports bits which are set for output mode will be latched and driven to the corresponding port pins, while data written to input bits will be ignored. The input DIO may be clocked externally by enabling the external digital clock bit in the appropriate configuration register. If the internal clock is used, the data is latched at the beginning of any read from the port.
About the X5 XMC Modules Since the bit I/O is not connected to the high speed data stream, this limits the effective update or read rate to about 1 MHz. Custom logic implementations can achieve much higher data rates by creating logic for data packets transfers to the Digital IO. The X5 FrameWork Logic user Guide details logic supporting the digital IO port and gives the pin information for customization.
About the X5 XMC Modules P16 Signal Virtex-5 FG1136 Pin Number Virtex-5 MGT Signal Identifier TXN4 L2 MGT_116_TXP1 RXP4 J1 MGT_116_RXN1 RXN4 K1 MGT_116_RXP1 TXP5 G2 MGT_116_ TXN0 TXN5 F2 MGT_116_TXP0 RXP5 H1 MGT_116_RXN0 RXN5 G1 MGT_116_RXP0 TXP6 AN9 MGT_126_ TXN1 TXN6 AN10 MGT_126_TXP1 RXP6 AP8 MGT_126_RXN1 RXN6 AP9 MGT_126_RXP1 TXP7 AN6 MGT_126_ TXN0 TXN7 AN5 MGT_126_TXP0 RXP7 AP7 MGT_126_RXN0 RXN7 AP6 MGT_126_RXP0 Figure 15.
About the X5 XMC Modules shutting down power to most of the X5 module. The host system power must be toggled in order to reset the module from this condition. The Framework Logic implements this feature as standard. Although it is possible for custom user logic to remove this feature, it is not recommended as it would expose the hardware to potential damage from over-temperature conditions, should they occur. The power enable signal is on Virtex-5 pin AF13. This pin must be held high to enable power.
About the X5 XMC Modules could be too little power resulting in the module failing or power glitches causing the temp sensor to drop out. Did other cards in the system fail? If so, this may indicate that a system problem must be solved. If the module did overheat, you should review the thermal design of the system.
About the X5 XMC Modules FrameWork Logic Many of the standard X5 XMC features are implemented in the application logic. This feature set includes a data flow, triggering features, and application-specific features. In many cases, this logic provides the features needed for a standard data acquisition function and is supported by software tools for data analysis and logging. In this manual, the FrameWork Logic features for each card are described in in general to explain the standard hardware functionality.
About the X5 XMC Modules Host Type Bus Mechanical Form-factor Adapter Required Example card adapter Compact PCI PCI Express 1.0a 3U CPCIe-XMC.3 adapter Innovative 80207 Cabled PCI Express PCI Express 1.0a Cabled PCI Express to remote IO Cable PCIe Adapter and XMC.
About the X5 XMC Modules The EEPROM application is straightforward to use: a Target board is selected, then an .EXO file is selected for reprogramming. The Target number tells the software which XMC module to program. If you have multiple XMC modules in the system, each has a unique Target number assigned by the software. If you don't know which card is which target, you can use the Finder program to blink the LED on each Target. Once you have selected the .
Writing Custom Applications Chapter 6: Writing Custom Applications Most scientific and engineering applications require the acquisition and storage of data for analysis after the fact. Even in cases where most data analysis is done in place, there is usually a requirement that some data be saved to monitor the system. In many cases a pure data that does no immediate processing is the most common application.
Writing Custom Applications compiler implements the GUI differently, each version of the example project uses the same file to interact with the hardware and acquire data. Program Design The Snap example is designed to allow repeated data reception operations on command from the host. As mentioned earlier, received data can be saved as Host disk files. When using modest sample rates, data can be logged to standard disk files.
Writing Custom Applications location in the PCI bus, so it will remain unchanged from run to run unless the board is moved to a different slot or another target is installed. Setup Tab This tab has a set of controls that hold the parameters for transmission. These settings are delivered to the target and configure the target accordingly. This tab has several sections. Clock section offers configurations and routing of the clock.
Writing Custom Applications displayed. This includes a count of the data blocks received, the data rate, the measured temperature of the board logic, and the digital I/O value. Host Side Program Organization The Malibu library is designed to be rebuildable in each of three different host environments: Codegear Developer's Studio C++ , Microsoft Visual Studio 2008, and on Linux.
Writing Custom Applications // // Member Data Innovative::X5_400M IUserInterface * Innovative::PacketStream IntArray unsigned int ii64 bool bool bool Innovative::StopWatch Innovative::DataLogger IntArray Innovative::BinView Innovative::Scripter float std::string Innovative::AveragedRate double std::string Innovative::SoftwareTimer ...
Writing Custom Applications // Alerts Module.Alerts().OnTimeStampRolloverAlert.SetEvent( this, &ApplicationIo::HandleTimestampRolloverAlert); Module.Alerts().OnSoftwareAlert.SetEvent(this, &ApplicationIo::HandleSoftwareAlert); Module.Alerts().OnWarningTemperature.SetEvent(this, &ApplicationIo::HandleWarningTempAlert); Module.Alerts().OnInputFifoOverrun.SetEvent(this, &ApplicationIo::HandleInputFifoOverrunAlert); Module.Alerts().OnInputTrigger.SetEvent(this, &ApplicationIo::HandleInputTriggerAlert); Module.
Writing Custom Applications Module.Target(Settings.Target); Module.Open(); Module.Reset(); UI->Status("Module Device Opened..."); Opened = true; This code shows how to open the device for streaming. Each baseboard has a unique code given in a PC. For instance, if there are three boards in a system, they will be targets 0,1 and 2. The order of the targets is determined by the location in the PCIe bus, so it will remain unchanged from run to run.
Writing Custom Applications { if (!StreamConnected) { UI->Log("Stream not connected! -- Open the boards"); return; } // // Make sure packets fit nicely in BM region. if (FBusmasterSize/16 < (unsigned int)Settings.PacketSize) { Log("Error: Packet size is larger than recommended size"); return; } // // Set up Parameters for Data Streaming // ...
Writing Custom Applications Module.Input().Info().Channels().DisableAll(); for (int i = 0; i < Channels(); ++i) { bool active = Settings.ActiveChannels[i] ? true : false; if (active==true) Module.Input().Info().Channels().Enabled(i, true); } X5_400M::IIClockSource src[] = { X5_400M::csExternal, X5_400M::csInternal }; Module.ClockSource(src[Settings.SampleClockSource]); int ActiveChannels = Module.Input().Info().Channels().
Writing Custom Applications // Set test mode Module.Input().TestEnable(Settings.TestCounterEnable); // Set Decimation Factor int factor = Settings.DecimationEnable ? Settings.DecimationFactor : 0; Module.Input().Decimation(factor); For test purposes, the FPGA firmware supports replacement of analog input samples with ascending ramp data. If the test counter is enabled in the GUI, it is applied to the hardware using the preceding code fragment.
Writing Custom Applications Handle Data Available Once streaming is enabled and the module is triggered, data flow will commence. Samples will be accumulated into the onboard FIFO, then they are bus-mastered to the Host PC into page-locked, driver-allocated memory following a two -word header (data packets). Upon receipt of a data packet, Malibu signals the Stream.OnDataAvailable event. By hooking this event, your application can perform processing on each acquired packet.
Writing Custom Applications The code fragment above calculates the nominal block processing rate. The AveragedRate object, Time, maintains a moving averaged filtered rate. This rate is stored in FBlockRate for use by display method of the GUI. if (Settings.LoggerEnable && !Logger.Logged()) { // Start counter Clock.Start(); std::stringstream msg; msg << "Packet size: " << Packet.Size() << " samples"; UI->Log(msg.str()); } // If enabled, log the data stream if (Settings.LoggerEnable || Settings.
Writing Custom Applications EEProm Access Each PMC module contains an IDROM region that can be used to read or write information associated with the module. In the next line of code we make a call to Malibu method IdRom(), which returns an object that acts as interface to that region. We further can query the ROM for its contents. Additional methods can be used to get more specific information.
Writing Custom Applications Module.Input().Calibrated(Settings.Calibrated); Module.IdRom().StoreToRom(); } The application code should test for NAN and in general for the validity of the received data. Please see Form1.h for MSVC .NET 2005 projects or Main.cpp for Borland 10 projects.
Writing Custom Applications User Interface The Linux OS supports a number of different windowing systems. We have chosen WxWidgets and DialogBlocks as an inexpensive, easy to use library and environment. Again, since the ApplicationIo object holds all the “program logic” for an application porting to a new environment is relatively straightforward. This application has five tabs. Each tab has its own significance and usage, though few are interrelated.
Writing Custom Applications Setup Tab This tab has a set of controls that hold the parameters for transmission. These settings are delivered to the target and configure the target accordingly. This tab has several sections. The Clock section offers configurations and routing of the clock. The clock for the FPGA can come from an external clock or from an internal crystal. The selection can be made at upper right corner of this section.
Writing Custom Applications Stream Tab The two buttons in the button bar start and stop data streaming. Press the running man button to start streaming data. Press the stop button to stop streaming, unless the stream has stopped itself. When streaming, the status bar data is collected and displayed. This includes a count of the data blocks received, the data rate, the measured temperature of the board logic, and the digital I/O value.
Writing Custom Applications void ApplicationIo::StartStreaming() { if (!FStreamConnected) { UI->Log("Stream not connected! -- Open the boards"); return; } // // Make sure packets fit nicely in BM region. if (FBmSizeWords/8 < (unsigned int)Settings.StreamPacketSize) { UI->Log("Error: Packet size is larger than recommended size"); return; } // // Set up Parameters for Data Streaming // ...First have UI get settings into our settings store UI->GetSettings(); if (Settings.TestEnable) { Module.Output().
Writing Custom Applications Module.Output().Decimation(factor); // All channels trigger together Module->Output().ExternalTrigger((Settings.ExternalTrigger == 1)); // Frame count in units of packet elements if (Settings.Framed) Module->Output().Framed(Settings.FrameCount); else Module->Output().Unframed(); Alerts and starting the Stream are the same as in Input only mode.
Writing Custom Applications //--------------------------------------------------------------------------// ApplicationIo::HandleDataRequired() //--------------------------------------------------------------------------void ApplicationIo::HandleDataRequired(PacketStreamDataEvent & Event) { SendOneBlock(Event.
Writing Custom Applications The Wave Example for Linux With the release of Linux support for Malibu and for Innovative products, there are versions of the example programs for this platform. This section discusses the Linux Wave example. The ApplicationIo Class Because we designed the original examples to separate Malibu and Baseboard functionality into a portable class, this code can move to the Linux example unchanged.
Developing Host Applications Chapter 7: Developing Host Applications Developing an application will more than likely involve using an integrated development environment (IDE) , also known as an integrated design environment or an integrated debugging environment. This is a type of computer software that assists computer programmers in developing software. The following sections will aid in the initial set-up of these applications in describing what needs to be set in Project Options or Project Properties.
Developing Host Applications Other considerations: Project Options ++ Compiler (bcc32) Output Settings check – Specify output directory for object files(-n) (release build) Release (debug build) Debug Paths and Defines add Malibu Pre-compiled headers uncheck everything Linker (ilink32) Output Settings check – Final output directory (release build) Release (debug build) Debug Paths and Defines (ensure that Build Configuration is set to All Configurations) add Lib/Bcb10 (change Build Configuration to Releas
Developing Host Applications Microsoft Visual Studio 2005 Microsoft Visual C++ 2005 (version 8) Project Properties When creating a new application with File, New, Project with Widows Forms Application: X5-GSPS User's Manual 68
Developing Host Applications Project Properties (Alt+F7) Configuration Properties C++ General Additional Include Directories Malibu PlotLab/Include – for graph/scope display Code Generation Run Time Library Multi-threaded Debug DLL (/Mdd) Precompiled Headers Create/Use Precompile Headers Not Using Precompiled Headers Linker Additional Library Directories Innovative\Lib\Vc8 If anything appears to be missing, view any of the example sample code Vc8 projects.
Developing Host Applications DialogBlocks DialogBLocks Project Settings (under Linux) Project Options [Configurations] Compiler name = GCC Build mode = Debug Unicode mode = ANSI Shared mode = Static Modularity = Modular GUI mode = GUI Toolkit = Runtime linking = Static or Dynamic, we use Static to facilitate execution of programs out of the box.
Applets Chapter 8: Applets The software release for a baseboard contains programs in addition to the example projects. These are collectively called “applets”. They provide a variety of services ranging from post analysis of acquired data to loading programs and logic to a full replacement host user interface. The applets provided with this release are described in this chapter. Shortcuts to these utilities are installed in Windows by the installation.
Applets Reserve Memory Applet (ReserveMemDsp.exe) Each Innovative PCI-based DSP baseboard requires 2 to 8 MB of memory to be reserved for its use, depending on the rates of bus-master transfer traffic which each baseboard will generate. Applications operating at transfer rates in excess of 20 MB/sec should reserve additional, contiguous busmaster memory to ensure gap-free data acquisition. To reserve this memory, the registry must be updated using the ReserveMemDsp applet.
Applets Logic Update Utility (VsProm.exe) The Logic Update Utility applet is designed to allow fieldupgrades of the logic firmware on the 210M module. The utility permits an embedded firmware logic update file to reprogrammed into the baseboard Flash ROM, which stores the "personality" of the board. Note that this utility should only be used after firmware development and debugging has been completed.
Applets Finder The Finder is designed to help correlate board target numbers against PCI slot numbers in systems employing multiple boards. Target Number Select the Target number of the board you wish to identify using the Target Number combo box. Blink Click the Blink button to blink the LED on the board for the specified target. It will continue blinking until you click Stop. On/OFF Use the On and Off buttons to activate or deactivate (respectively) the LED on the baseboard for the specified target.
X5-GSPS XMC Module Chapter 9: X5-GSPS XMC Module Introduction The X5-GSPS is a member of the X5 XMC family that has two channels of 8-bit 1.5 GSPS A/D conversion with DC coupled inputs. The two channels can be used as one 8-bit 3 GSPS A/D in a special double-rate mode. The X5-GSPSP has a high performance computing core for signal processing, data buffering and system IO is built around a Virtex-5 FPGA.
X5-GSPS XMC Module Figure 17. X5-GSPS Module (analog cover and heat sink removed) Custom application logic development for the X5-GSPS is supported by the FrameWork Logic system from Innovative using VHDL and/or MATLAB Simulink. Signal processing, data analysis, and application-specific algorithms may be developed for use in the X5-GSPS logic and integrated with the hardware using the FrameWork Logic.
X5-GSPS XMC Module Figure 18. X5-GSPS Block Diagram Hardware Features A/D Converters The X5-GSPS has two channels of 8-bit A/D sampling at up to 1.5 GSPS. The A/D has an interleaved sample mode that allows one channel to sample at up to 3 GSPS. Minimum sample rate is 200 MHz, below which severely degraded performance occurs. . The X5-GSPS implements a DC-coupled or AC-coupled, 50 ohm terminated SMA connector-based front end.
X5-GSPS XMC Module Feature Description Inputs 2 Input Range +1V to -1V single-ended Input Coupling DC Input Impedance 50 ohm A/D Devices National Semiconductor ADC08D1500 (Rev A) National Semiconductor ADC08D1520 (Rev B) Output Format 2's complement, 8-bit Number of A/D Devices 2 simultaneously sampling Sample Rate 200-1500 MSPS Calibration Factory calibrated. Gain and offset errors are digitally corrected in logic. Non-volatile EEPROM coefficient memory. Table 13.
X5-GSPS XMC Module Figure 19. X5-GSPS A/D Channel 0 Front End Figure 20. X5-GSPS A/D Channel 1 Front End Input bandwidth measurement is shown in the data section of this chapter. Input Range and Conversion Codes Each A/D input has a +1V to -1V single-ended input with 50 ohm input impedance. Other input ranges may be custom ordered. Data output codes from the A/D system is 2's complement. The following table gives the transfer function. Input voltage (V+-V-) Conversion Code (hex) +1 0x7F +0.
X5-GSPS XMC Module Driving the A/D Inputs The X5-GSPS has single-ended, DC coupled inputs that are 50 ohm terminated. The 50 ohm termination is used to match the input cable and connector characteristic impedance. The source signal must be able to drive this input impedance to achieve the best signal quality over the input voltage range. The signal source must be able to drive +/- 20mA for a full scale input.
X5-GSPS XMC Module The external clock input at connector J4 is AC coupled and can accept either sine wave or digital clock sources. The following table gives the electrical requirements for the clock input. Feature Description Input Impedance 50 ohm Input Coupling AC Input Connector SMA Minimum Input Swing 200mVp-p (-20.8 dBm) Maximum Input Swing 2.0Vp-p (-0.8 dBm) Maximum Frequency Supports converter maximum clock rates (1.5 GHz) Jitter <0.5 ps, pk-pk Figure 22.
X5-GSPS XMC Module On the X5-GSPS module, both A/D channels operate synchronously using the same clock and trigger. The trigger controls allows data to be acquired continuously, or during a specified time, as triggered by either a software or external trigger. Data can also be decimated to reduce data rates.
X5-GSPS XMC Module Framed Trigger Mode Framed trigger mode is useful for collecting data sets of a fixed size each time the input trigger is fired. In framed mode, the trigger goes false once the programmed number of points N have been collected. Start triggers that occur during a frame trigger are ignored. The maximum number of points per frame is 16,777,216 (2^24) points, while the minimum number of points is 8. Frame size must be a multiple of 8 on the X5-GSPS.
X5-GSPS XMC Module 2 channels Figure 25. X5-GSPS FrameWork Logic Data Flow The data flow is driven by the data acquisition process . Data flows from the A/D devices into the A/D interface component in the FPGA as controlled by the triggering. The data is then error corrected and the enabled channels flow to the data buffer. The data buffer implements a data queue in the DRAM.
X5-GSPS XMC Module operating temperatures. This requirement is highly application dependent and must be evaluated for each application and installation. If forced air cooling is not used, conduction cooling is another method of dissipating the module heat. A thermal plane in the card is attached to thermal conduction surfaces on each side of the module. The card can then be cooled by mounting the card on host card that supports conduction cooling per VITA specification 20.
X5-GSPS XMC Module shut down if necessary because thermal overload may be coming. Better to shut down than crash in most cases. The temperature failure alert tells the system that the module actually shut itself down. This usually requires that the module be restarted when conditions permit. The data acquisition alerts, including over ranges, overflows and triggering, tell the system that important events occurred in the data acquisition process.
X5-GSPS XMC Module Since alert packets contain status words such as temperature for each packet, a software alert can essentially be used to read temperature of the module and so that it can be recorded. Software Support for Alerts Applications have different needs for alert processing. Aside from the bulk movement of data, most applications require some means of handling special conditions such as post-processing upon receipt of a stop trigger or closing a driver when an acquisition is completed.
X5-GSPS XMC Module Calibration coefficients for gain should not be outside the range of 0.95 to 1.05, and offset should not be outside the range of +/-400 counts for the A/Ds . If the calculated coefficients are larger than this, they are either wrong or the channel is damaged. Using the X5-GSPS Where to start? The best place to start with the X5-GSPS module is to install the module and use the SNAP example to acquire some data.
X5-GSPS XMC Module Performance Data Power Consumption The X5-GSPS requires the following power for typical operation with when using the FrameWork Logic. This typical number assumes a 250 MHz system clock rate and 125 MSPS A/D and D/A data rates for the application logic. Table 17. X5-GSPS Power Consumption Voltage Maximum Allowed Current (A) Typical Current Required (A) Typical Derived from Power (W) Supplies these Devices 3.3V 15 5.1A 16.
X5-GSPS XMC Module Environmental Table 18. X5-GSPS Environmental Limits Condition Limits Operating Ambient Temperature 0 to 55 C Humidity 5 to 95 %, non condensing Storage Temperature -30 to 85 C Forced Air Cooling Dependent on application Vibration, operating ETS 300 019- 1.3 [R3], class 3.3 Vibration, storage ETS 300 019- 1.1 [R1], class 1.2 Vibration, transportation ETS 300 019- 1.2 [R2], class 2.3 except for free-fall: class 2.
X5-GSPS XMC Module Test Group Parameter Measured Units Test Conditions Analog Response Bandwidth 820 MHz -3 dB, 500 mVp-p sine Amplitude Variation 1 dB 10 to 650 MHz, 500 mVp-p sine Analog Input Response Analog Input Response 2 0 1 -0.5 0 -1 -1 -1.5 -2 dB -3 dB dB dB -2 -2.5 -3 -4 -3.5 -5 -4 -6 -4.5 -7 10 100 1000 550 600 650 700 750 800 850 900 950 Frequenc y (MH z ) Frequency (MHz) Figure 26.
X5-GSPS XMC Module Figure 28. X5-GSPS Ground Noise, Fs = 125 MSPS, input grounded Figure 29.
X5-GSPS XMC Module Figure 30. X5-GSPS A/D Signal Quality vs. Input Amplitude Signal Quality vs Input Amplitude 60 50 S/N(dB) SFDR(dB) SINAD(dB) dB 40 30 20 10 0 0 0.5 1 1.5 Input Amplitude (Vp-p) Input Amplitude(V) 2 1 0.5 0.1 X5-GSPS User's Manual S/N(dB) 41.2 38.7 31.3 17.6 2 2.5 SFDR(dB) 48.1 43.3 34.1 20.6 SINAD(dB) 40.1 38 31.1 17.
X5-GSPS XMC Module Signal Quality vs Sample Rate 52 50 48 dB 46 S/N(dB) SFDR(dB) SINAD(dB) 44 42 40 38 637.5 700 850 900 998.3313001497.5 Sample Rate (MHz) Fin = 101 MHz, filtered, 2Vp-p Sample Rate (MHz) 637.5 700 850 900 998.33 1300 1497.5 S/N(dB) 43.8 43.4 43.2 43.7 43.7 43.1 44 SFDR(dB) 48.6 48 48.3 47.9 49.9 48.8 49.2 SINAD(dB) 43.7 43.2 43.1 42.8 43.5 42.9 43.6 Figure 31.
X5-GSPS XMC Module Figure 1. Signal Quality, Fin = 101 MHz, 2Vp-p, Fs = 1497.5 MSPS, DC Coupled SFDR =49.2 dB ENOB= 7.0 bits Fin = 101Hz, 2Vp-p Fs = 1497.
X5-GSPS XMC Module Figure 2. Signal Quality, Fin = 101 MHz, 2Vp-p, Fs = 1497.
X5-GSPS XMC Module S/N = 43.8 dB SINAD = 43.7 dB SFDR = 48.6 dB ENOB = 7.0 bits THD = -78.1 dB Fin = 101MHz, 2Vp-p Fs = 637.5 MSPS Figure 3. Signal Quality, Fin = 101 MHz, 2Vp-p, Fs = 637.5 MSPS, DC Coupled Connectors RF Connectors J1-J4 J1-J2connectors are positioned on the front panel for analog input, clock and trigger signals to be connected to the module.
X5-GSPS XMC Module Connector Type: SMA 50 ohm Number of Connections: 1 per signal Connector Part Number Amphenol 901-143 Mating Connector: Amphenol 901-9511-3 or equivalent Cable Innovative part number 67048 SMA to BNC cable Connector Function J1 A/D channel 0 J2 A/D channel 1 J3 Trigger input J4 Clock input Figure 4. Connectors J1-J4 Functions XMC P15 Connector P15 is the XMC PCI Express connector to the host.
X5-GSPS XMC Module Connector Types: XMC pin header, 0.05 in pin spacing, vertical mount Number of Connections: 114, arranged as 6 rows of 19 pins each Connector Part Number Samtec ASP-105885-01 Mating Connector: Samtec ASP-105884-01 Figure 5.
X5-GSPS XMC Module Column Row A B C D E F 1 PET0p0 PET0n0 3.3V PET0p1 PET0n1 VPWR 2 GND GND GND GND MRSTI# 3 PET0p2 PET0n2 PET0p3 PET0n3 VPWR 4 GND GND GND GND MRSTO# 5 PET0p4 PET0n4 PET0p5 PET0n5 VPWR 6 GND GND GND GND +12V 7 PET0p6 PET0n6 PET0p7 PET0n7 VPWR 8 GND GND GND GND -12V 3.3V 3.3V 3.3V 9 VPWR 10 GND GND GND GND GA0 11 PER0p0 PER0n0 MBIST# PER0p1 PER0n1 VPWR 12 GND GND GA1 GND GND MPRESENT# 13 PER0p2 PER0n2 3.
X5-GSPS XMC Module Table 21.
X5-GSPS XMC Module Figure 6.
X5-GSPS XMC Module Table 22.
X5-GSPS XMC Module Table 23. P16 Signal Descriptions Signal Description DIO0-15 Digital IO 0-15 TXP0-7 SERDES transmit positive TXN0-7 SERDES transmit negative RXP0-7 SERDES receive positive RXN0-7 SERDES receive negative Xilinx JTAG Connector JP1 is used for the Xilinx JTAG chain. It connects directly with Xilinx JTAG cables such as Parallel Cable IV or Platform USB.
X5-GSPS XMC Module Table 24. X5-GSPS JP3 Xilinx JTAG Connector Pinout Pin Signal Direction 1,3,5,7,9,11,13 Digital Ground Power 2 1.8V Power 4 TMS I 6 TCK I 8 TDO O 10 TDI I 12,14 No Connect - Mechanicals The following diagrams show the X5-GSPS connectors and physical locations. The XMC conforms to IEEE 1386 form factor, 75mm x 150mm. The spacing to the host card is 10 mm and consumes a single slot in desktop and Compact PCI/PXI chassis.
X5-GSPS XMC Module M2.
X5-GSPS XMC Module Figure 9. X5-GSPS Mechanicals (Top View) Rev A Figure 10.
