Datasheet

ManualsBrandsCypress Semiconductor ManualsComputer equipmentCY7C141

36-Mbit QDR

II SRAM 2-Word

Burst Architecture

CY7C1412BV18

CY7C1414BV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-07036 Rev. *E Revised August 24, 2009

Features

■ Separate independent Read and Write Data Ports

❐ Supports concurrent transactions

■ 250 MHz clock for high bandwidth

■ 2-word burst on all accesses

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 500 MHz) at 250 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR

II operates with 1.5 cycle read latency when Delay Lock

Loop (DLL) is enabled

■ Operates as a QDR I device with 1 cycle read latency in DLL

off mode

■ Available in x 18, and x 36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8V (±0.1V); I/O V

DDQ

= 1.4V to V

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1412BV18 – 2M x 18

CY7C1414BV18 – 1M x 36

Functional Description

The CY7C1412BV18, and CY7C1414BV18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR II archi-

tecture. QDR II architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. QDR II

architecture has separate data inputs and data outputs to

completely eliminate the need to ‘turnaround’ the data bus

required with common I/O devices. Access to each port is

accomplished through a common address bus. The read

address is latched on the rising edge of the K clock and the write

address is latched on the rising edge of the K

clock. Accesses to

the QDR II read and write ports are completely independent of

one another. To maximize data throughput, both read and write

ports are provided with DDR interfaces. Each address location

is associated with two 18-bit words (CY7C1412BV18), or 36-bit

words (CY7C1414BV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus ‘turnarounds’.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz

Maximum Operating Current x18 850 725 650 mA

x36 1000 850 740

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Summary of content (24 pages)

PAGE 1
CY7C1412BV18 CY7C1414BV18 36-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations ■ Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1412BV18 – 2M x 18 CY7C1414BV18 – 1M x 36 ■ 250 MHz clock for high bandwidth Functional Description ■ 2-word burst on all accesses ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges
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CY7C1412BV18 CY7C1414BV18 Logic Block Diagram (CY7C1412BV18) K CLK Gen. DOFF 20 Address Register Read Add. Decode K Write Reg 1M x 18 Array Address Register Write Reg 1M x 18 Array A(19:0) 20 18 Write Add. Decode D[17:0] A(19:0) RPS Control Logic C Read Data Reg. C CQ 36 VREF WPS BWS[1:0] 18 Control Logic 18 Reg. Reg. 18 Reg. 18 CQ 18 Q[17:0] Logic Block Diagram (CY7C1414BV18) K CLK Gen. DOFF 19 Address Register Read Add.
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CY7C1412BV18 CY7C1414BV18 Pin Configuration The pin configuration for CY7C1412BV18 and CY7C1414BV18 follow.[1] 165-Ball FBGA (15 x 17 x 1.
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CY7C1412BV18 CY7C1414BV18 Pin Definitions Pin Name I/O Pin Description D[x:0] InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. Synchronous CY7C1412BV18 - D[17:0] CY7C1414BV18 - D[35:0] WPS InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
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CY7C1412BV18 CY7C1414BV18 Pin Definitions Pin Name DOFF (continued) I/O Pin Description Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off.
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CY7C1412BV18 CY7C1414BV18 Functional Overview The CY7C1412BV18, and CY7C1414BV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required.
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CY7C1412BV18 CY7C1414BV18 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V.
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CY7C1412BV18 CY7C1414BV18 Truth Table The truth table for CY7C1412BV18, and CY7C1414BV18 follows.[2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising edge of K; input write data on K and K rising edges. L-H X L D(A + 0) at K(t) ↑ Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges.
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CY7C1412BV18 CY7C1414BV18 Write Cycle Descriptions The write cycle description table for CY7C1414BV18 follows.[2, 8] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document #: 001-07036 Rev.
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CY7C1412BV18 CY7C1414BV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
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CY7C1412BV18 CY7C1414BV18 IDCODE BYPASS The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state.
PAGE 12
CY7C1412BV18 CY7C1414BV18 TAP Controller State Diagram The state diagram for the TAP controller follows.[9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 PAUSE-DR 0 0 0 1 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-07036 Rev.
PAGE 13
CY7C1412BV18 CY7C1414BV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[10, 11, 12] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V VOH2 Output HIGH Voltage IOH = −100 μA 1.
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CY7C1412BV18 CY7C1414BV18 TAP AC Switching Characteristics Over the Operating Range[13, 14] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns 50 n
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CY7C1412BV18 CY7C1414BV18 Identification Register Definitions Value Instruction Field Description CY7C1412BV18 CY7C1414BV18 000 000 Cypress Device ID (28:12) 11010011010010111 11010011010100111 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Revision Number (31:29) Version number. Defines the type of SRAM.
PAGE 16
CY7C1412BV18 CY7C1414BV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 3M 11 10N 39 11D 67 1C 95 12 9P 40 9C 6
PAGE 17
CY7C1412BV18 CY7C1414BV18 Power Up Sequence in QDR II SRAM DLL Constraints QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior.
PAGE 18
CY7C1412BV18 CY7C1414BV18 Maximum Ratings Neutron Soft Error Immunity Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Parameter Description Test Conditions Typ Storage Temperature ................................. –65°C to +150°C LSBU Logical Single-Bit Upsets 25°C 320 368 FIT/ Mb LMBU Logical Multi-Bit Upsets 25°C 0 0.01 FIT/ Mb Single Event Latch up 85°C 0 0.1 FIT/ Dev Ambient Temperature with Power Applied..
PAGE 19
CY7C1412BV18 CY7C1414BV18 Electrical Characteristics (continued) DC Electrical Characteristics Over the Operating Range[12] Parameter Description ISB1 Automatic Power down Current Test Conditions Max VDD, 250 MHz Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL 200 MHz f = fMAX = 1/tCYC, Inputs Static 167 MHz Min Typ Max 420 475 370 420 345 390 Unit mA Min Typ Max Unit (x18) (x36) (x18) (x36) (x18) (x36) AC Electrical Characteristics Over the Operating Range[11] Parameter Description Test Condi
PAGE 20
CY7C1412BV18 CY7C1414BV18 Switching Characteristics Over the Operating Range[20, 21] Cypress Consortium Parameter Parameter Description VDD(Typical) to the First Access [22] tPOWER 250 MHz 200 MHz 167 MHz Min Max Min Max Min Max 1 1 1 Unit ms tCYC tKHKH K Clock and C Clock Cycle Time 4.0 8.4 5.0 8.4 6.0 8.4 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 1.6 – 2.0 – 2.4 – ns tKL tKLKH Input Clock (K/K and C/C) LOW 1.6 – 2.0 – 2.
PAGE 21
CY7C1412BV18 CY7C1414BV18 Switching Waveforms Figure 5.
PAGE 22
CY7C1412BV18 CY7C1414BV18 Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors.
PAGE 23
CY7C1412BV18 CY7C1414BV18 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195 BOTTOM VIEW TOP VIEW Ø0.25 M C A B +0.14 (165X) -0.06 Ø0.50 1 PIN 1 CORNER Ø0.05 M C PIN 1 CORNER 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 10.00 B 15.00±0.10 0.15 C 0.35±0.06 0.53±0.05 0.25 C 0.
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CY7C1412BV18 CY7C1414BV18 Document History Page Document Title: CY7C1412BV18/CY7C1414BV18, 36-Mbit QDR® II SRAM 2-Word Burst Architecture Document Number: 001-07036 REV. ECN NO. Submission Date Orig.