Specifications

Hardware Implementation
Figure 8 is the schematic for a dual-interface keyboard application. This design may be used to implement a USB-only
keyboard, a dual-interface (USB and PS/2) keyboard, or a USB keyboard with the capability to support a slave PS/2 mouse.
The latter design is the subject of Cypress Application Note XXXXX. The table in the lower left hand corner of the schematic
Main Drawing shows what components are to be installed for the desired implementation
Key Matrix and LEDs
Port 2 is configured as resistive (7 Kohm pull-ups to Vcc), and is connected to rows 0~7 of the scan matrix, providing
support for up to 8 rows. Port 0, 1, and 3 are also configured as resistive. Ports 0 and 1 provide connection to key matrix
columns 0 ~ 15, and coulmns 16 and 17 are serviced by Port 3 bits 4 and 5, providing support for up to 18 columns. For
scan matrices with less than 8 rows or 18 columns, the unused port bits may be left unconnected. The cathodes of the three
keyboard LEDs (Num Lock, Caps Lock, and Scroll Lock) are connected via current-limiting resistors R7, R8 and R9 to bits 0,
1 and 2 of Port 3, which can sink sufficient current to directly drive the LEDs. The LED anodes are connected directly to
VCC. An LED is turned ON by the firmware writing a 0 to its corresponding port bit.
When no row or column bits are set to 0 by the firmware, all bits will be pulled to a logic ‘1’ by their internal 7K-ohm
resistors. When, during key scanning, firmware drives any column bit to a logic ‘0’, the row bits corresponding to any closed
keys on that column in the matrix will also be read as logic 0’s by the firmware. If no keys are closed on the activated
column, all row bits will be read as logic 1’s by the firmware. See Figure 7. Each column in the matrix is scanned by writing
its associated port bit to logic 0, holding all other column bits at logic 1, then interrogating the row inputs on port 2. A
complete matrix scan consists of one scan for each column in the matrix.
Power-On Reset
Port 3, Bit 7 controls the POR mode of the CY7C63413 microcontroller. Depending upon the interface being implemented,
this bit will be pulled either to VCC, invoking suspend-mode POR, or to GND, invoking run-mode POR. Suspend mode POR
is used when the host interface is known to be USB. In this mode, the microcontroller goes immediately into a suspend state
after power-on, until a USB Reset condition is detected on the D+/D- lines. Upon detection of this condition, the
microcontroller institutes a 128uS delay, after which code execution begins.
In the case where the host interface is know to be or may be PS/2, and therefore in which a USB Reset condition may not
occur, run-mode POR is selected. In this mode, the microcontroller, upon detection of power, implements a 128mS delay for
power and oscillator stabilization, after which code execution begins.
Microcontroller Clock
The microcontroller clock in the refertence design is based on a 6 MHz ceramic resonator which is connected across the
XTALI and XTALO pins of the microcontroller. The CY7C63413 includes internal DC biasing and crystal element load
capacitance together with an inverting amplifier to implement an on-chip Colpitts-style inverting oscillator using the external
crystal or resonator. This circuit is intended to operate using no other external components with crystals or resonators
designed for a parallel-resonant load capacitance of 30pF. As the XTALI pin is a high-impedance node, the resonator or
crystal component should be placed as physically close to the microcontroller as possible, and care should be taken in
layout to avoid coupling of high-frequency signals onto this node. The 6MHz reference clock produced by the oscillator
circuit is frequency doubled, using an on-chip phase-locked loop (PLL), to yield the 12MHz CPU instruction clock.
Power
The 5V Vcc and GND come directly from the host interface cable. Shield ground is also provided on the host connector. A
4.7uF tantalum capcitor, C3, provides bulk power supply bypass, and additional high-frequency bypass is provided by 0.1uF
capacitor C2. Capacitor C4 provides an AC path between signal ground and shield ground, per the USB specification, and
10M-ohm resistor R10 is provided as a DC discharge path for C4 in the event that shield ground and signal ground become
separated at the host.
Host Interface Connection
In the event that the host interface is known to be USB, jumper JP1 will be installed, connecting resistor R2 between the
USB D- line and Vcc. The USB specification indicates that a 1.5K-ohm, 5% resistor be used between the D- line and a 3.0 ~
3.6V DC rail for termination of a low-speed device. The reference design employs a 1%, 7.5K-ohm resistor between D- and