User manual

CY8C24223A, CY8C24423A
Document Number: 38-12029 Rev. *H Page 21 of 34
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 20. AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
F
IMO24
Internal Main Oscillator Frequency for
24 MHz
23.04
[12]
24 24.96
[12]
MHz Trimmed using factory trim
values.
F
CPU1
CPU Frequency (5V Vdd Nominal) 0.09
[12]
12 12.48
[12]
MHz
F
24M
Digital PSoC Block Frequency 0 24 24.96
[12, 13]
MHz
F
32K1
Internal Low Speed Oscillator
Frequency
15 32 64 kHz This specification applies when
the ILO has been trimmed.
F
32KU
Internal Low Speed Oscillator (ILO)
Untrimmed Frequency
5 – – kHz After a reset and before the
M8C processor starts to
execute, the ILO is not trimmed.
F
32K2
External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
F
PLL
PLL Frequency – 23.986 – MHz A multiple (x732) of crystal
frequency.
Jitter24M2 24 MHz Period Jitter (PLL) – – 800 ps Refer to Figure 9 on page 22.
T
PLLSLEW
PLL Lock Time 0.5 – 10 ms Refer to Figure 6 on page 22.
T
PLLSLEWSLOW
PLL Lock Time for Low Gain Setting 0.5 – 50 ms Refer to Figure 7 on page 22.
T
OS
External Crystal Oscillator Startup to
1%
– 1700 2620 ms Refer to Figure 8 on page 22.
T
OSACC
External Crystal Oscillator Startup to
100 ppm
– 2800 3800 ms
Jitter32k 32 kHz Period Jitter – 100 – ns Refer to Figure 10 on page 22.
T
XRST
External Reset Pulse Width 10 – – μs
DC24M 24 MHz Duty Cycle 40 50 60 %
DC
ILO
Internal Low Speed Oscillator (ILO)
Duty Cycle
20 50 80 %
Step24M 24 MHz Trim Step Size – 50 – kHz
Jitter24M1P 24 MHz Period Jitter (IMO)
Peak-to-Peak
– 600 – ps Refer to Figure 9 on page 22.
Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean
Squared
– – 600 ps
F
MAX
Maximum frequency of signal on row
input or row output.
– – 12.48
[12]
MHz
SR
POWERUP
Power Supply Slew Rate – – 250 V/ms Vdd slew rate during power up.
T
POWERUP
Time between end of POR state and
CPU code execution
– 16 100 ms Power up from 0V.
Notes
12. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
13. See the individual user module data sheets for information on maximum frequencies for user modules.
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