IDE Guide Document # 001-42655 Rev *B Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.
Copyrights Copyrights Copyright © 2002-2009 Cypress Semiconductor Corporation. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights.
Contents 1. Introduction 1.1 1.2 1.3 1.4 1.5 1.6 7 Application Overview ................................................................................................................8 1.1.1 Chip-Level Editor...........................................................................................................8 1.1.2 System-Level Editor ......................................................................................................9 1.1.3 Code Editor ..........................................
Copyrights 2.12.1 Working with ISRs ...................................................................................................... 49 2.12.2 Interrupt Vectors and the Chip-Level Editor ................................................................ 50 2.13 Dynamic Reconfiguration ....................................................................................................... 52 2.13.1 Adding Configurations .....................................................................................
4.2 4.1.3 boot.asm .....................................................................................................................90 4.1.4 main.asm/main.c .........................................................................................................90 4.1.5 PSoCConfig.asm.........................................................................................................90 4.1.6 Additional Generated Files..................................................................................
Copyrights 7.7 7.6.4 Debug Strategies for I2C Debugger ..........................................................................125 7.6.5 Break Points..............................................................................................................125 7.6.6 Watch Variables ........................................................................................................126 Programming the Part ..............................................................................................
1. Introduction PSoC Designer™ is two tools in one. It combines a full featured integrated development environment (IDE) (the Chip-Level Editor) with a powerful visual programming interface (the System-Level Editor). The two tools require and support two different design processes: In the Chip-Level Editor you specify exactly how you want the device configured.
Introduction 1.1 Application Overview PSoC Designer contains several subsystems: Chip-Level Editor, System-Level Editor, Code Editor, Build Manager, Project Manager, Board Monitor, and Debugger. The interface is split into several active windows that differ depending upon which subsystem you are in. As you move between subsystems, different options are enabled or disabled in the toolbar and menus depending upon the functionality of your PSoC device. 1.1.
Introduction 1.1.2 System-Level Editor The PSoC Designer System-Level Editor contains three desktops: Design, Simulation, and Monitor, which are selectable with the four subtabs shown in Figure 1-2. When you select each of the different tabs, the look and use of the main area changes to accommodate the specifics of that desktop. The default window layout contains the Driver Catalog, Workspace Explorer, Properties, and Datasheet Windows.
Introduction from the View menu that show details of different aspects of PSoC Designer. You can rearrange the work area to suit your own work style. Figure 1-3. PSoC Designer Code Editor 1.1.4 Build Manager The Build Manager is a largely invisible utility that controls the various portions of the build process including the compiler (or compilers), assembler, and linker, and manages the process of building your project and preparing it to download to a target device.
Introduction 1.1.6 Debugger The debugger has multiple windows that allow you to interact with and observe the code execution on the target PSoC device. The debugger is tightly integrated with the rest of the IDE, and there is no separate debugger view. Instead, there are a number of different windows that you can use to monitor the status of various parts of your target board while debugging, including the following: 1.1.
Introduction Table 1-1. Chapter Overviews (continued) Chapter 1.3 Description Assembler In this chapter you receive high-level guidance on programming assembly language source files for the PSoC device. Build Manager In this chapter you learn the details of building a project, discover more about the C Compiler as well as the basic, transparent functions of the system Linker and Loader, and Librarian.
Introduction Table 1-2. Documentation Conventions (continued) Convention [bracketed, bold] Usage Displays keyboard commands in procedures: [Enter] or [Ctrl] [C] File > New Project Represents menu paths: File > New Project > Clone Bold Displays commands, menu paths and selections, and icon names in procedures: Click the Debugger icon, and then click Next. Text in gray boxes 1.4.1 Displays cautions or functionality unique to PSoC Designer or the PSoC device.
Introduction 1.5 References This guide is part of a larger documentation suite for the PSoC Designer application. It is meant as a reference, not as the complete source of information. For the most up-to-date information, go to http://www.cypress.com. The documentation listed here provides more specific information on a variety of topics: 1.
2. Chip-Level Editor The Chip-Level Editor allows you to work directly with the resources available on a PSoC device, select and configure user modules, such as analog to digital converters (ADCs), timers, amplifiers, and others, and route inputs, outputs, and other resources to and from them. Figure 2-1.
Chip-Level Editor 2.1 Chip-Level Editor Overview The Chip-Level Editor gives you complete control over Chip-Level Projects resource use, routing, and firmware. You choose a specific chip at the beginning of this process: 1. Create a Project This is the first step in both processes, but after naming your project, the first thing that you do in a Chip-Level Project is select a PSoC device. 2. Select a PSoC Device There are a large number of PSoC devices in the PSoC family with more being added all the time.
Chip-Level Editor 2.2 Create a Project In order to program the desired functionality into a PSoC device, you need to first create a project directory in which the files and device configurations reside. 1. To start a new project, select New Project from the File menu. Figure 2-2. New Project Dialog Box The System-Level Editor creates a special environment that allows it to generate all necessary program code based on the elements and logic in the System-Level Project.
Chip-Level Editor 3. In the Select Project Type dialog box, click View Catalog to access a detailed list of available parts. Figure 2-3. Create New Project Dialog Box 4. In the Parts Catalog Dialog Box, highlight your part of choice. Tabs at the left and characteristic selections along the top narrow the list of devices. You have several options in this dialog box including layout display, viewing part image, and sorting part selection (by clicking on a chosen column title).
Chip-Level Editor 6. Click OK. Your workspace directory with folders is created and is listed in the Workspace Explorer. If the Workspace Explorer is not visible, choose Workspace Explorer from the View menu. 2.2.1 Clone a Project Cloning a project is used when you want to convert an existing project to a different PSoC part. The part is referred to as the “base” part.
Chip-Level Editor data sheet when you click on a user module, select View > Datasheet Window. Right-click on the user module and select Place. Some user modules have wizards or configuration screens that appear before the user module can be placed. These will differ by user module. The user module will be placed in the first available PSoC block in the Interconnect view. The user module block reference names appear above the currently active blocks.
Chip-Level Editor If user modules are already placed, then there are some cases when user module placement fails even if it appears that sufficient PSoC blocks remain unallocated. In such cases, the already placed user modules are using resources that the selected user module requires. There are several user modules that require topology selection (i.e., filters). Right-click on the module in the Aplication Explorer after it is placed and click User Module Selection Options.
Chip-Level Editor 1. Click each drop-arrow (in parameter value fields) and make your selections. Some parameters are integer values. Set these values by clicking the up/down arrows, or doubleclick the value and type in the value. If you type a value that is out of range, an error message appears in the lower-left corner. 2. Repeat this process for all placed user modules. 2.3.
Chip-Level Editor 32K_Select The 32K_Select parameter allows selection of the internal 32 kHz oscillator or an external crystal oscillator. A complete discussion of the implications of this selection is found in the PSoC Technical Reference Manual. A_Buf_Power A_Buf_Power allows the user to select the power level for the analog output buffers of the PSoC. These buffers are used to supply internal analog signals to external pins on the PSoC.
Chip-Level Editor CLKOUT Source Selects one of the clocks, internal SysClk, external, low power 32 KHz, or CPUCLK to be output directly on port P0[1]. CPU_Clock The CPU_Clock selection allows the selection of the M8C clock speed from 93.75 kHz to 24 MHz. The CPU clock is derived directly from the SysClock. Use an external 32 kHz oscillator and the PLL Ext_Lock to improve clock accuracy. A discussion of the main oscillator is contained in the PSoC Technical Reference Manual.
Chip-Level Editor Power Setting [Vdd/SysClock Freq] This parameter allows you to select the SysClock frequency and nominal operating voltage. Based upon the SysClock selected, the Internal Main Oscillator (IMO) is set with appropriate calibration settings. Since many internal clocks are derived from the SysClock, you see significant device powerconsumption savings by lowering the SysClock frequency, if the implemented design permits it.
Chip-Level Editor Trip Voltage [LVD (SMP)] A precision POR circuit is integrated into the PSoC. This parameter allows the user to select voltage levels that the PSoC uses to internally monitor its supply voltage. Two levels are specified in the parameter with the syntax . LVD is the value at which the internal low voltage comparator asserts its control signal. SMP is the level at which the integrated switch mode pump is enabled.
Chip-Level Editor Designer. A complete discussion of the relation of the sleep and watchdog timers is in the PSoC Technical Reference Manual. 2.4 Project Backup Folder PSoC Designer maintains a backup folder in the project directory for files that were removed from the source tree. This includes files that are manually removed and files removed due to cloning or code generation. The backup folder only retains the version of the file that was last removed.
Chip-Level Editor 2.5.1 Connecting User Modules These procedures show you how to make certain types of connections. Global In Global In connections apply to a PSoC device in this manner: CY8C25xxx/26xxx as Global In: Input Port Connections. All other PSoC devices as Global In Odd and Global In Even: Input Port Connections and Global Connections. To set Global In connections: 1. Click on the target Globalxxx vertical line. 2. Select the pin to connect to. 3.
Chip-Level Editor 1. Click on the target Globalxxx vertical line. 2. Select the global input to output connection (if active) and the port. 3. Click OK. You see a line connecting the digital output port to the global vertical line. Analog Clock Select To set Analog Clock Select connections: 1. Click on the target AnalogClock_x_Select Mux. Figure 2-6. The AnalogClock_0_Select Mux 2. Select a DBAxx or DBBxx PSoC block (as applies).
Chip-Level Editor 1. Click on the target AnalogColumn_Clock_x Mux. Figure 2-8. Setting the AnalogColumn_Clock_0 Mux 2. Select a device-specific option from the menu. You see that the AnalogColumn_Clock_x Mux has a line connecting your chosen option to the mux output. Analog Column Input Mux To set Analog Column Input Mux connections: 1. Click on the target AnalogColumn_InputMUX_x. Figure 2-9. Setting the AnalogColumn_InputMUX_3 2. Select a port from the menu.
Chip-Level Editor Analog Output Buffer The Analog Output Buffers can be connected to the associated port pin or turned off. To set Analog Output Buffer connections: 1. Click on the target AnalogOutBuf_x. Figure 2-11. Setting the AnalogOutBuf_2 2. Select a port from the menu. You see a line that connects the AnalogOutBuf_x triangle to the analog output port. Clock Input for a Digital Block To set Clock Input connections on a digital block: 1.
Chip-Level Editor Enable Input for a Digital Block To set the Enable Input connection on a digital block: 1. Click the Enable text label on the digital block where your target user module is placed. Note that the name Enable Input is determined by a specified user module parameter. Figure 2-13. Setting the Enable Input for an 8-bit Counter User Module 2. Select an option from the menu. You see your chosen input option displayed next to the Enable text label.
Chip-Level Editor RBotMux for a CT Analog Block To select a RBotMux for a CT Analog Block, follow this procedure. You can use this procedure when the NMux, PMux, AnalogBus, or CompBus CT Analog Block apply, as well as for ACMux, BMux, AnalogBus, or CompBus SC Analog Blocks. 1. Click the RBotMux text label on the analog block where your target user module was placed. Note that the name RBotMux is determined by a specified user module parameter. Figure 2-15.
Chip-Level Editor Comparator Analog LUT Comparator Analog LUT connections do not apply to CY8C25xxx/26xxx parts. To set Comparator Analog LUT connections: 1. Click the AnalogLUT_x box. (Its symbol is identified in the Comparator x line along each column of analog PSoC blocks.) 2. Select an option from the menu. You see connections on the device interface reflecting your A or B selection with associated symbols. 2.5.
Chip-Level Editor Input vertical line.) In this floating window you can also click the white box to toggle the Synchronization value for Row_x_Input_x. Options include SysClk_Sync and Async Figure 2-18. Synchronization Options for Digital Interconnect Row Inputs 3. Click Close when finished. 2.5.3 Digital Interconnect Row Output Window Digital Interconnect Row Output Window connections do not apply to CY8C25xxx/26xxx parts. Row Logic Table Input To set Row Logic Table Input connections: 1.
Chip-Level Editor Row Logic Table Select To set Row Logic Table Select connections: 1. Click on the target Row_x_Output_x Logic Table Box. 2. Click on the Row_x_LogicTable_Select_x logical operation box in the Digital Interconnect Row Output floating window and select an option from the menu Figure 2-20. Logical Operations in Digital Interconnect Row Output 3. Click Close when finished. You see connections on the device interface reflecting your A or B input selection with associated symbol.
Chip-Level Editor Once you open the Digital Interconnect Row Global Output window, you can select Row Logic Table Input, Row Logic Table Select, and Connections to Global Output without closing the window. Figure 2-21. Digital Interconnect Row Global Output 3. Click the Close button when finished. You see a connection from the Row_x_Output_x Logic Table Box to the chosen GlobalOutEven_x vertical line. 2.6 Specifying the Pinout Specifying the pinouts is the next step to configuring your target device.
Chip-Level Editor Analog Input To set Analog Input connections. 1. Click on the target Port_0_x. 2. From the Select menu select AnalogInput. Figure 2-22. Select AnalogInput for a Port 3. Click OK. On the device you see the new designation color coded according to the legend along side the device. The port name and selection also appears in the port-related fields underneath User Module Parameters (where you can click the drop-arrow to change your selection).
Chip-Level Editor Global_IN_x Global_IN_x connections apply to a PSoC device in this manner: CY8C25xxx/26xxx as Global_IN_x. All other PSoC devices as GlobalIn[Odd/Even]_x. To set Global_IN_x connections: 1. Click on the target Port_x_x. 2. From the Select menu select the device-specific Global IN option. Figure 2-24. Select Global IN for a Port 3. Click OK. On the device you see the designation color coded according to the legend next to the device.
Chip-Level Editor StdCPU To set StdCPU connections: 1. Click on the target Port_x_x or select the port from the menu. 2. From the Select menu select StdCPU. Figure 2-26. Select StdCPU for a Port 3. Click OK. On the device you see the designation color coded according to the legend next to the device. The port name and StdCPU also appear in the port-related fields underneath User Module Parameters (where you can click the drop-arrow to change your selection). XtalOut To set the XtalOut connection: 1.
Chip-Level Editor 2. From the Select menu select XtalIn. Figure 2-28. Select CXtalOut for Port 1 1 3. Click OK. On the device you see the designation color coded according to the legend next to the device. The port name, XtalIn, and the drive mode of High Z also appear in the port-related fields underneath User Module Parameters (where you can click the drop-arrow to change your selection). ExternalGND To set the ExternalGND connection: 1. Click on Port_2_4 (P2[4]) or select Port_2_4 from the menu. 2.
Chip-Level Editor On the device you see the designation color coded according to the legend next to the device. The port name and Ext Ref also appear in the port-related fields underneath User Module Parameters (where you can click the drop-arrow to change your selection). In the device interface you see that all lines from P2[6] are gone. I2C SDA To set the I2C SDA connection (this connection is only available for CY8C27xxx parts): 1. Click on Port_1_5 (P1[5]) or select P1[5] from the menu. 2.
Chip-Level Editor Click the pin and make settings in the device pinout Change port-related fields in the Global or User Module properties windows Port drive modes apply to a PSoC device in this manner: CY8C25xxx/26xxx options include High Z, Pull Down, Pull Up, and Strong. All other PSoC device options include High Z, High Z Analog, Open Drain High, Open Drain Low, Pull Down, Pull Up, Strong, and Strong Slow. To specify a port drive mode: 1. Click on the target Port_x_x. 2.
Chip-Level Editor 3. Click OK. The port name and DisableInt appears in the port-related fields underneath User Module Parameters (where you can click the drop-arrows to change your selections). FallingEdge To specify FallingEdge interrupt: 1. Click on the target Port_x_x. 2. From the Interrupt menu select FallingEdge. Figure 2-35. Set Port Interrupt to Falling Edge 3. Click OK.
Chip-Level Editor The resource meter tracks Analog Blocks, Digital Blocks, RAM, ROM, and the use of device specific special resources such as the decimator, CapSense™ blocks, or I2C controller. As you place user modules, you can view how many analog and digital PSoC blocks you have available and how many you have used. RAM and ROM monitors track the amount RAM and ROM required to employ each selected user module. Figure 2-37. PSoC Block Resource Meter 2.
Chip-Level Editor You can run the DRC at any time or any number of times during project development. To run it automatically each time you generate application files, go to: Tools > Options > Interconnect Editor > General. You can also set specifics regarding the level of rule checking and result detail, go to: Tools > Options > Tools > DRC tab. 2.9 Generating Application Files Generating application files is the final step to configuring your target device.
Chip-Level Editor 2.10 Source Files Generated by Generate Project Operation Table 2-1 lists and describes the source files generated by the Generate Project operation. Table 2-1. Source Files Generated by Generate Application Name Overwritten Description …/lib/PSoCConfig.asm Yes Configuration loaded upon system access …/lib/PSoCCOnfigTBL.asm Yes Contains chip configuration Boot.asm Yes Boot code and initial interrupt table …/lib/.
Chip-Level Editor strings if you safely define the interrupt vector and install your own handler. If there is no interrupt handler for a particular interrupt vector, the comment string “// call void_handler” is inserted in place of the substitution string. NOTE: If you install an interrupt handler and make changes directly to boot.asm, the changes are not preserved if application generation is executed after you make the changes. If you make changes to boot.
Chip-Level Editor an .h file for configurations of a 16-bit PWM (Pulse Width Modulator) created during application-code generation: Figure 2-40. PWM_FAN0.h Once you generate the device configuration application code, the files for APIs and ISRs are located in the source tree of Workspace Explorer under the Library Source Files and Library Header Files folders.
Chip-Level Editor 4 Analog Columns VC3 GPIO 16 Digital Blocks I2C Sleep Timer The configurable interrupts include 16 digital blocks and 4 analog columns. The definition (for example, interrupt vector action) of a configurable interrupt depends on the user module that occupies the block or uses the analog column.
Chip-Level Editor When the application is generated, code is produced for the Timer32_1 User Module. The interrupt vector table is also altered with the addition of the call to the timer interrupt handler in boot.asm.
Chip-Level Editor Table 2-2. boot.
Chip-Level Editor 1. Right click the Loadable Configuration folder in the Workspace Explorer and select New Loadable Configuration. Figure 2-43. Add a New Loadable Configuration 2. You see a new folder with a default name of Configx where x is the number of alternate configurations. Select the configuration folders to switch from one configuration to the other. There is always at least one folder with the project name when a project is created. This folder represents the base configuration.
Chip-Level Editor 2.13.3 Renaming Configurations To rename a loadable configuration in your PSoC project: 1. Right click the loadable configuration and click Rename. 2. Type the new name. 3. Press [Enter] or click your cursor somewhere outside the folder. 2.13.4 Employing Dynamic Reconfiguration These sections discuss how global parameters, pin settings, and code generation are dynamically reconfigured. 2.13.4.
Chip-Level Editor CustomPinName_DriveMode_0_ADDR CustomPinName_DriveMode_1_ADDR CustomPinName_IntCtrl_0_ADDR CustomPinName_IntCtrl_1_ADDR The CustomPinName used in the substitution is replaced by the name entered for the pin during code generation. Custom pin naming allows you to change the name of the pin. The name field is included in the pin parameter area of the pinout diagram. The Name column in the Pin Parameter Grid shows the names assigned to each of the pins.
Chip-Level Editor restore the base configuration user modules. The ReloadConfig_xxx function ensures the integrity of the write only shadow registers. Respective load tables are generated for these functions in the PSoCConfigTBL.asm file. An additional unload function is generated UnloadConfig_Total function loads these tables: UnloadConfigTBL_Total_Bank0 UnloadConfigTBL_Total_Bank1 as UnloadConfig_Total. The These tables include the unload registers and values for all PSoC blocks.
Chip-Level Editor 2.13.4.5 PSoCDynamic Files Three files are generated when additional configurations are present in a project: PSoCDynamic.inc PSoCDynamic.asm PSoCDynamicINT.asm PSoCDynamic.inc The PSoCDynamic.inc file is always generated. It contains a set of equates that represent the bit position in the active configuration status variable, and the offset to index the byte in which the status bit resides, if the number of configurations exceeds eight.
Chip-Level Editor 58 If an overlapping configuration is loaded and then unloaded, register labels from the original configuration will be used, even though some PSoC blocks will have been cleared by the last UnloadConfig routine.
3. System-Level Editor The System-Level Editor allows you to select and configure various design elements, such as inputs, outputs, valuators, and interfaces. This desktop is where you create your designs. The main area is empty when you create a new project. The top contains the toolbar. The areas surrounding the design area are configurable, and can contain a variety of windows available from the View menu. Figure 3-1.
System-Level Editor 3.1 System-Level Editor Overview The System-Level Editor gives you the ability to rapidly create a project in a visual design environment that represents the way you think about the design: Inputs, Outputs, Logic, and Communication. These are represented in PSoC Designer’s Express interface as Inputs, Outputs, Valuators, and Interfaces. 1. Create a Project Your first step is to create a new project in PSoC Designer.
System-Level Editor 3.2 Create a New Project Click File → New Project, or [Ctrl] + [Shift] + [N], to start with a new blank design. You will be prompted to name and save your design immediately. 3.2.1 Add Design Elements You create designs by selecting the tab that contains the type of design element you want to add (Inputs, Outputs, Valuators, or Interfaces) from the Driver Catalog, see Figure 3-2, and then dragging and dropping elements from the Driver catalog, see Figure 3-2. Figure 3-2.
System-Level Editor As you go through the Drivers and Valuators list in the Driver Catalog, A Current Device Description window (Figure 3-3) opens and provides information about the most recent device you have selected. If you do not see the window, choose Datasheet Window from the View menu. Figure 3-3. Current Device Description Window Immediately after you release the driver on the desktop, the Add Output Driver window appears.
System-Level Editor 3.2.3 Replace – Brings up a catalog of drivers and lets you replace the existing driver with the one chosen from the catalog (not applicable to valuators). Use Navigation Tools Some designs get large, and elements may not all fit in the same desktop. You can press and hold [Ctrl] and click the mouse to zoom in, press and hold [Ctrl] + [Shift] and click the mouse to zoom out, and press and hold [Alt] and drag the mouse to Pan. 3.2.
System-Level Editor 3.2.5 Delete Elements To delete any element, including text labels and boxes, right click on the element and select Delete. You can also select an element and press [Delete]. 3.2.6 Save a Design You have three options when saving your project: 3.3 Click Save, [Ctrl] + [S] Select File → Save As Click Save All, which saves all open projects Simulating Your Design The Simulation desktop (Figure 3-6) allows you to simulate your design. Figure 3-6.
System-Level Editor 3.3.3 LOG.csv File When you run simulation manually, PSoC Designer creates a simulation log file in comma separated or value format called LOG.csv. This file contains columns for the input values and the output values. Each row of the simulation file represents one iteration of the control loop. You may edit this file offline using Excel or any other CSV compatible spreadsheet program.
System-Level Editor Output drivers implement these transfer functions: PriorityEncoder StatusEncoder TableLookup See “Transfer Functions” on page 67 for a description of these functions. 3.4.1.3 Input/Output Driver Input/Output drivers combine input and output functionality. They provide the ability to both get and set the driver’s value. Typical Input/Output drivers include: 3.4.1.
System-Level Editor StateMachine – The new output state is based upon the current state and the result of evaluating all transition expressions associated with the current state. StatusEncoder – The output value depends upon all input conditions that evaluate true. The conditions are evaluated from top to bottom in order. TableLookup – The output value is defined by the combinations of inputs states. Not all combinations need to set the output.
System-Level Editor 3.6.1.4 PriorityEncoder A PriorityEncoder provides a method to generate a single output value using only the highest priority true input. PriorityEncoders are often used to combine multiple hierarchical input states into a single valuator. For example, use a PriorityEncoder to command a fan to turn at the certain speed commanded by multiple temperature input sensors.
System-Level Editor Table 3-1. C Operators Supported in the LiteralCode Transfer Function Operator Type Math Bitwise Conditional Unary + & ? + Supported Operators – * / % | ^ << >> && || < > <= >= = ~ ! Local variable declaration. Read only access to project variables and values. Math functions. Table 3-2.
System-Level Editor 3.8 Selecting a Configuration The first step in building your design is to select a configuration. Click Build and the PSoC Device Configuration Selection window displays, as shown below. Figure 3-7. PSoC Device Configuration Selection Window There are three main parts to this window: a list of available device configurations, configuration properties, and a description of the selected configuration.
System-Level Editor 3.8.2 BOM Vendor This pull down list allows you to select a specific vendor (or none) to view the bill of materials (BOM). Some vendors participate in an agreement with Cypress so that once your design is complete you can order the necessary parts automatically. 3.8.3 Assign Pins Automatically This check box allows PSoC Designer to assign the pins for you. 3.9 If you check this box and click OK, the build process begins immediately.
System-Level Editor lighted in green. The green highlighting indicates that those pins will accept the driver you assigned. Drop the blue rectangle on any one of these pins. When you finish assigning pins, click Next for the last step in the build process. 3.9.1 Pin Color Legend When you select and drag a driver, all pins are outlined in one of three colors: green, orange, or black. Green indicates the pin is a legal placement and unblocked.
System-Level Editor When the hex file generation is complete, PSoC Designer compiles the design and programming information into a set of custom reports, and then presents the information on the BOM/Schematic desktop. Figure 3-9. BOM/Schematic Desktop . The BOM Schematic desktop shows the resulting pin assignments on the device. The desktop also includes hypertext links to the BOM, data sheet, and schematic custom created for your design. Click on any hyperlink to view the output in a separate window. 3.
System-Level Editor 1. Open PSoC Designer 2. Create a new project with an appropriate name. 3.
System-Level Editor For this example select CY8C29466, 28-Pin PDIP/SSOP/SOIC. Make certain to select Assign pins automatically. Click OK. 6. When the build system completes you see this screen. Automatic pin assignment failed because of conflicts between the drivers. You now begin the process of manually assigning drivers to the unassigned pins so that you solve this problem. Now you place the unassigned drivers on of the available pins.
System-Level Editor 7. Clear all pin assignments by clicking the Unassign All Pins button. The result is a screen that looks like this. All the drivers are now listed on the right of the screen as unassigned drivers. 8. When you click a driver the ports to which you can assign it are highlighted in green. Begin with LED_bit0. 9. Drag InterfaceSlave_i2c I2CsCLPin to pin 13. The SDAPin will automatically assign to pin 15.
System-Level Editor 10.Select each of the other drivers and repeat the process until all the drivers are assigned and the screen looks like this. The build is now complete and you are ready to move to the next step: programming the part. The process illustrated here seems simple. You add inputs, outputs, and an interface. Then you select a part and build the file. If there are conflicts such as encountered in this example you reassign the drivers and complete the process.
System-Level Editor Table 3-3. PSoC Designer and PSoC Designer 4.3 Design Views PSoC Express PSoC Designer 4.4 Your seemingly simple design is, in fact, complex and ready for further customization. 3.12 Programming PSoC Flash Memory When you are satisfied with your design and completed build, you need to program and test your PSoC device. Click Program to launch the PSoC Programmer application. Figure 3-10.
System-Level Editor The application loads with the PSoC Designer hex file in memory. Follow instructions in the PSoC Programmer User Guide to program the PSoC device. When you are done programming, exit the PSoC Programmer application. Not exiting the application may cause some communication errors between PSoC Designer and PSoC Programmer. 3.
System-Level Editor The monitor desktop looks very similar to the simulation desktop, except that you are monitoring live values from your prototype board. The board monitor also enables the use of the variables chart window that allows you to track any or all of your system variables in real time. Figure 3-12. Variables Chart Window The variables chart allows you to track all or any combination of system variables in real time on a chart.
System-Level Editor 2. If your design does not already have an I2C interface, choose an I2C slave communication interface, and place it on your design. Leave the I2C_Address at the default value of 4. 3. When you do pin assignment for the project, the I2C pins will default to P1[7] and P1[5]. You will need to move them to P1[0] and P1[1]. 4. Build your project and program your board. 5. Switch to the Monitor desktop. 6. Plug the I2C-USB Bridge into your board. 7.
System-Level Editor 11. Interacting with the controls on the board will register in the board monitor in real time. 3.13.2 Monitoring Your Board with Other Interfaces If you use USB, or some other interface in your design, you will need to write your own firmware to communicate with the board monitor. 3.14 Tuning Your Design Most drivers in PSoC Designer are very simple. They have a few easily modifiable parameters, the results of which are easy to predict.
System-Level Editor 2. Make sure that the Flash Interface is Enabled in the Device Configuration properties when you choose the device for your project. Exposing tuning values adds some extra code to your design, so you may want to make sure that you set Expose Tuning Values to No before you do your final build, especially if resources are tight or you are trying to fit your final design into a smaller, less expensive part. The following example shows the process of tuning a driver.
System-Level Editor The tuner window for the driver displays. 2. Touch the button on the board that corresponds to driver tuner displayed. The button is more sensitive than it needs to be. 3. Increase the Finger Threshold and increase the IDAC setting. The IDAC setting is inversely related to the sensitivity of the button. See driver datasheet for more information about the settings. 4. Click Apply to Board to write the changed parameter to Flash on the PSoC device.
System-Level Editor 5. To see exactly where a button triggers you can move your finger slowly on to the button. Do this to observe that the Finger Threshold is higher now than it was before. 6. Place a finger fully on the button to observe that it is less sensitive now. 7. Click OK to save the values from the tuner window back to properties in PSoC Designer. Clicking Cancel discards your changes, and retains the original properties settings.
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4. Code Editor In this chapter you learn how to create the project code. 4.1 File Definitions and Recommendations Once you complete your device configuration, you are ready to create the application code. This is done in the Code Editor subsystem. To access the Code Editor, double click any source file in the Workspace Explorer. Figure 4-1. Code Editor View The Workspace Explorer is shown in the right frame of Figure 4-1.
Code Editor 4.1.1 File Types and Extensions When you create a project, a root directory with three folders is generated at the location you specify. The name of the root directory is the project name and the names of the three folders are lib (Library), obj (Objects), and output (for files generated by a project build). ■ The lib folder contains user module Library Source files. ■ The obj folder contains intermediate files generated during the compiling/assembling of .c and assembly source files.
Code Editor Table 4-1. File Types and Extensions (continued) Type Extension Location Description ROM File .rom …\output folder under project directory This file is a legacy (M8A M8B) program image output file. Template .tpl Project directory Editable template file. Templatea .tpl Installation directory under …\Templates then copied to project directory Template files used to generate project files (boot.tpl > boot.asm). Text Document .
Code Editor assembled and linked source, they are read only. You can also access the Output tab on the source tree in the Code Editor by selecting Tools > Options > Code Editor tab and unchecking Enable Output. 4.1.3 boot.asm This startup file resides in the source tree under Source Files and is important because it defines the boot sequence. The components of the boot sequence are: ■ Defines and allocates the reset and interrupt vectors. ■ Initializes device configuration.
Code Editor The registerName registers vary with the chip device description and include all registers associated with the GPIO ports.
Code Editor 4.2 Working in Code Editor Before you begin adding and modifying files, take a few moments to navigate Code Editor, take inventory of your current files, and map out what you plan to do and how you plan to do it. 4.2.1 Modifying Files When you are ready to program and modify assembly language source files, double-click the target file located in the file source tree. The file opens and appears in the main active window. You can open multiple files simultaneously.
Code Editor 4.2.2 Adding New Files To add a file: 1. Click the New File icon or select File > New File. 2. In the New File dialog box, select a file from the File types. 3. In the Name field, type the name for the file. 4. The current project directory is the default destination for your file. Uncheck the Add to current project field and click Browse to identify a different location if you do not want the default. The Browse button is only enabled if you uncheck the Add to current project field.
Code Editor 4.2.5 Searching Files In addition to the standard Find/Replace feature in PSoC Designer, you can search for specific text inside specific files. To search for text in any single file or combination of multiple files: 1. Click Edit > Find and Replace. Figure 4-4. Find and Replace Dialog Box 2. In the Find what field of the Find in Files dialog box, type or click the drop-arrow to choose a previously searched word. Search by standard grep (Global Regular Expression Print) methods.
5. Assembler In this chapter you receive high-level guidance on programming assembly language source files for the PSoC device. For comprehensive details, see the PSoC Designer Assembly Language User Guide. 5.1 Accessing the Assembler The assembler is an application accessed from within PSoC Designer, much like the C Compiler. This application is run as a batch process. It operates on assembly language source to produce executable code.
Assembler 5.2.1 Address Spaces There are three separate address spaces implemented in the Assembler: ■ Register Space (REG) – Accessed through the MOV and LOGICAL instructions. There are 8 address bits available to access the register space, plus an extended address bit via the Flag register bit 4. ■ Data RAM Space – Contains the data/program stack and space for variable storage. All the read and write instructions, as well as instructions which operate on the stacks, use data RAM space.
Assembler 5.2.4 Destination of Instruction Results The result of a given instruction is stored in the destination, which is placed next to the opcode in the assembly code. This allows for a given result to be stored in a location other than the accumulator. Direct and indexed addressed data RAM locations, as well as the X register, are additional destinations for some instructions.
Assembler 5.5 Assembler Directives The PSoC Designer Assembler allows the assembler directives listed in Table 5-4. See the PSoC Designer Assembly Language User Guide for descriptions and sample listings of supported assembler directives. Table 5-4. Assembler Directives Symbol AREA ASCIZ BLK BLKW DB DS DSU DW DWL ELSE ENDIF EQU EXPORT IF INCLUDE .LITERAL, .ENDLITERAL MACRO/ENDM ORG .SECTION, .
Assembler 5.6 Instruction Set To access a complete instruction in detail within PSoC Designer, click your cursor on the target instruction in the file and press [F1]. Table 5-5 lists the notation used for the instructions. See the PSoC Designer Assembly Language User Guide for the complete instruction set. Table 5-5. Instruction Set Notation Notation A CF expr F k k1 k2 PC SP X ZF 5.
Assembler The Output Status (or error-tracking) window of Code Editor is where the status of file compiling and assembling resides. Each time you compile and assemble files, the Output Status window is cleared and the current status is entered as the process occurs. Figure 5-1. Output Status Window When compiling is complete, you the see the number of errors. Zero errors signify that the compilation and assemblage was successful. One or more errors indicate problems with one or more files.
Assembler For example, an assembly function that is passed a single byte as a parameter and has no return value looks like this: C function declaration (typically in a .h header file) #pragma fastcall16 send_byte void send_byte( char val); C function call (in a .c file) send_byte( 0x37); Assembly function definition (in an .
Assembler Functions with more complex input parameters or return values can be written using these tables. Table 5-6. Pragma Fastcall16 Conventions for Argument Passing Argument Type Single Byte Two Single Bytes Double Byte Pointer Register A A, X X, A A, X All Others None Argument Register The argument is passed in A. The first argument is passed in A, the second in X. The MSB is passed in X, the LSB in A. The MSB is passed in A, the LSB in X.
6. Build Manager In this chapter you learn the details of building a project, discover more about the C Compiler as well as the basic, transparent functions of the system Linker and Loader, and Librarian. For comprehensive details on the C Compiler, see the PSoC Designer C Language Compiler User Guide. 6.1 Building a Project Building a project compiles and assembles all source files and selectively assembles library source files.
Build Manager Each time you build your project, the Output Status window in Code Editor is cleared and the current status is entered as the process occurs. Figure 6-1. Output Status Window When the build is complete, you see the number of errors and warnings. Zero errors signify a successful build. One or more errors indicate problems with one or more files. If there are errors, the program image (.hex file) is available for download to the ICE.
Build Manager ■ The Enable Paging checkbox is used to enable or disable large memory model appliations (applications using more than 256 bytes of RAM) on target chips with more than 256 bytes of RAM. Unchecking this box for these chip restricts RAM usage to the first 256 bytes and decreases program execution time and size associated with manipulating RAM paging registers. ■ Stack Page is an indicator of the RAM page on which the stack will be allocated for a large memory model application.
Build Manager 6.3.1 ImageCraft Specific Linker Options Configuration options of imagecraft specific linker are as follows: ■ Relocatable code start address specifies the first Flash address for the linker to start placing relocatable code areas. This address may be entered in decimal or hexadecimal but is displayed in decimal. ■ Object/library modules specifies a list of libraries to link in addition to the default library.
Build Manager 6.4 Librarian The library and archiving features of PSoC Designer provide system storage and reference. There are two types of Librarian files (located in the source tree): Library Source and Library Headers. Source file types include archived and assembly language such as libPSoc.a and PSocConfig.asm. Header files are intermediate reference and include files created during application code generation and compilation.
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7. Debugger In this chapter you learn how to download your project to the In-Circuit Emulator (ICE), use debug strategies, and program the part. For additional information about the ICE and the development kit, refer to Application Note AN2018, Care and Feeding of ICE Pods at http://www.cypress.com/. Some PSoC devices do not use an external emulator (ICE cube or ICE-4000) for debugging. Instead, the PSoC Designer I2C Debugger debugs on-chip through a 5-pin ISSP header and MiniProg3.
Debugger The PSoC ICE User Guide teaches you how to connect the ICE to your computer, configure the software to enable communication and debugging between PSoC Designer and the Pod, and troubleshoot the ICE installation. The PSoC Programmer User Guide (referred in 7.7 “Programming the Part“ on page 130) teaches you how to open a HEX file, select a communication port, set a device, set a programming mode, program, verify, read, and run a checksum.
Debugger 7.2 Menu Options The Debugger and ICE toolbars incorporate the most important Debugger functions. A listing of all Debugger menu options is available in Table 7-1. The I2C debugger does not use an external emulator and does not support the following: ■ Events Window ■ Trace Window ■ Trace Mode All other debug functions are fully supported. Table 7-1.
Debugger 7.3 Connecting to the ICE You must establish a communication link between the PC and the ICE. This is done by choosing the appropriate ‘port’. To make the Debugger port selection select the Project > Settings > Debugger tab. Figure 7-2. Debugger Project Settings - LPT1 The “ICE connected to:” list shows parallel ports (i.e., LPT1…3) supporting the original PSoC ICE.
Debugger menu item. The results of the connection attempt are displayed in the Output window. A successful connection displays this message: Connecting . . . ICE Port: USB/0611C003 Pod powered by the ICE Connected. The status bar shown in Figure 7-3 also shows information associated with debugging. Figure 7-3. Debug Status Bar. 7.4 Downloading to the Pod Before you begin a debug session you need to download your project .hex file to the pod.
Debugger 7.5 Debug Strategies Debugger commands allow you to read and write program and data memory, read and write IO registers, read and write CPU registers and RAM, set and clear breakpoints, and provide program run, halt, and step control. Figure 7-4.
Debugger To help with troubleshooting, you can view your application source files inside the Debugger subsystem. If the project source tree is not showing, click View > Workspace Explorer. The project files that you view in the debugger will be read-only while the debugger is running or halted at a breakpoint. The source files are editable when the debugger is reset. 7.5.1 Trace The Trace feature enables you to track and log device activity at either a high or detailed level.
Debugger The trace log entries are logged before the instruction is executed. The contents of those entries are: ■ PC Register ■ A Register ■ Data Bus ■ External Signals When using the ICE-4000, the external input value is the binary representation of the 8 center pins on the 10-pin ICE header. The right and left outside pins are connected to ground while the inputs accept a 5-volt TTL level signal. The time stamp is displayed as a 32-bit relative count of clock cycles from the CPU clock source.
Debugger 7.5.3 CPU and Register Views There are five areas that are readable and writable during debugging: CPU Registers, Bank Registers 0, Bank Registers 1, RAM, and Flash. The CPU Registers are shown in their own window (Debug > Windows > Registers) and in the notification area at the bottom of PSoC Designer. The other four areas can be viewed in the Memory Window (Debug > Windows > Memory). Select one of the four memory areas from the Address Space box. Each is described below.
Debugger 7.5.4 Watch Variables Watch Variables can be set by right clicking a variable in a source file and selecting Add Watch. You can also select Global Variables. Right-click Add, Delete, or Properties in the Watch/Global Name window to add, delete, or modify values. Note that if you change a variable type (or other settings in the window) and close the project, the next time you access that project the variable types and settings are the same. Figure 7-8.
Debugger 7.5.4.1 Array Types Added to Global and Local Watch Variables Array types were added to both Global and Local Watch Variables. Global and Local Watch Variable array types must originate in C and not be exported from an .asm file. For example: //-------------------------------char sC[5]; signed char signedC[5]; int siI[5]; unsigned int uiI[5]; float fA[5]; long slL[5]; unsigned long uslL[5]; //------------------------------The example above shows declarations for all the supported array types.
Debugger 4. Fill in the applicable thread fields (i.e., Low Compare, Input Select, High Compare, Input Mask), as well as state logic fields (i.e., Next State, Match Count). As you make your selection in the Input Select drop-down, you see details in the grayed-out, scrollable box below. Also, use Match Count to specify the number of times an event task occurs before it performs the selected action.
Debugger 7.5.5.3 Event Examples Here are a few examples for common events. Find Memory Write To break on a memory write to address 20h, execute the following example steps. 1. Access the Debugger Events dialog box by clicking Debug > Windows > Events. 2. Choose BITFIELD in the Parameter box. The small help box in the lower left describes the BITFIELD input. Bit 1 is the RAM write flag. 3. Bit 1 is the focus bit of this example; therefore, you need to mask the other bits.
Debugger 1. Access the Debugger Events dialog box by clicking Debug > Events. Figure 7-9. Stack Overflow Events Dialog Box 2. Set the Input select drop-down to SP. 3. Set both the Low compare and High compare values to 00FF. 4. Check the Break check box in the State Logic fields. 5. Click Apply, then close the Events window.
Debugger 12.Set Input select to A, Low compare and High compare to 32, and leave the Input Mask at FF. 13.Under State Logic set Next state to 3, the Match Count to 10, and check Trace Off and Break. 14.Click Apply to save, then close the Events window. 7.5.6 End Point Data If your project includes one of the USB user modules, you can display USB endpoint data captured from the emulator in a debug window. To do so, select Debug > Windows > USB Endpoint Data. This creates a file named USB Data.
Debugger 7.6 I2C Debugger 7.6.1 Connecting to the ICE An important setting for each PSoC Designer project is the ICE Device that will be used for debugging. For I2C debugging you will need to select the MiniProg3 from the list of ICE Devices in the Project > Settings > Debugger tab. The ICE Device list shows only hardware that can be used for the project that is currently opened. MiniProg3 can support up to 100mA in 5V, 3.3V, 2.5V, 1.8V, or you can choose to supply the power externally.
Debugger cally. A hex file generated with Debug Mode enabled will not run on the PSoC device unless it is connected to the Debugger. Before generating production code, disable debug mode. Figure 7-12. Debug Mode Enabled 7.6.3 Downloading to the Device Before you begin a debug session you need to download your project .hex file to the target device. To download the .hex file to the device: 1. Click the Download to Emulator (Pod) icon . The system downloads the project .
Debugger The I2C Debugger doesn’t use the external emulator and has a limited number of break points. Active Break points will be shown with solid icon as shown in Figure 7-13: Figure 7-13. Breakpoints Window 7.6.6 Watch Variables The WatchWindow subsystem distinguishes between watch variables that were declared in the project source code and watch variables that were created through the Watch Window pop-up menu, Define arbitrary watch.
Debugger Table 7-2. Data Display versus Format Format Types of Data that Can be Displayed Hexadecimal All Data Types Binary All Data Types ASCII One-byte data types - char and unsigned char Unicode Two-byte data types - int, unsigned int, short, unsigned short, pointer Usually, the contents of the watch variable's memory location are displayed and modifiable in the Value field. There are two conditions when the data is not displayed in the Value field: 1.
Debugger To display a single element or field of an array or struct, select just that element from the Watch Window and then edit the format of just that element. Figure 7-16. Items Displayed in their Configured Data Formats The image of the Watch Window shown in Figure 7-17 shows a single watch variable named yStruct, of type YourStruct. It contains 4 fields named myStruct, msArray, iArray and f. The display format of the msArray field is set to Binary.
Debugger Checking the Hexadecimal item in the Watch Window's pop-up menu toggles all data in the window to hexadecimal format. When Hexadecimal is un-checked, the data formats return to their original display format. Figure 7-17. Items Displayed in Hexadecimal Format Note that when the native format of an item has been set to Hexadecimal, toggling the Watch Window Hexadecimal setting will appear to have no effect on that item. 7.6.6.
Debugger 7.7 Programming the Part Programming the part is done once debugging is complete. By doing this, you store the ROM data directly in the Flash memory of the part. The Cypress device can be reprogrammed many times due to its Flash Program Memory. Figure 7-18 shows the Pod Programming Socket that is connected to a CAT5 cable. Only the five required serial programming pins are available on the programming socket.
Debugger Alternatively, the device can be programmed on the target board using the Serial Programming Header on the Pod. The five connections that must be made from the Serial Programming Header to the pins on the target device are listed in Table 7-3. Table 7-3.
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8. Flash Protection Flash Program Memory Protection (FPMP) allows you to select one of four protection (or security) modes for each 64-byte block within the Flash, based upon the particular application. 8.1 FPMP and PSoC Designer PSoC Designer has a rudimentary mechanism that enables you to set security modes in your Flash program memory. The security (or protection) is set from within PSoC Designer on a per project basis.
Flash Protection 8.2 About flashsecurity.txt The FPMP file, flashsecurity.txt, is added to each new project and appears in the Workspace Explorer. Figure 8-1. flashsecurity.txt in Source Tree PSoC Designer also adds the FPMP file to a cloned project. This is especially useful when cloning projects created with earlier versions of PSoC Designer because earlier versions did not carry this feature.
Flash Protection Figure 8-2 is an example of a flashsecuriy.txt file. Figure 8-2. Example of flashsecurity.txt 8.3 FPMP File Errors PSoC Designer lets you know when FPMP file errors occur. A dialog box appears, if you edit or enter the wrong information in the flashsecurity.txt file, when you are downloading to the ICE or programming a part. A message also appears in the Build tab of the Output Status window. Figure 8-3.
Flash Protection For example, if you have a Flash data table that can be changed using a Flash write routine, you might have assembly code that looks like this: area Table (ROM, ABS) org 3C80h widgetTable: export WidgetTable db 57h ; W db 49h ; I db 44h ; D db 47h ; G db 45h ; E db 54h ; T ; …. More table entries continue You then unprotect the Flash block associated with this table at address 3C80h and make your change in the flashsecurity.txt file as shown in Figure 8-4. Figure 8-4.
Appendix A. Troubleshooting This appendix presents solutions for some potential system problems. A.1 Troubleshooting the Chip-Level Editor Problem: You cannot read the fine print in the User Interface that shows the interconnect view. Solution: Place the cursor in the center of the diagram. Right-click the mouse and select Zoom In from the menu. You can also hold the CTRL key and click the image itself Figure 1-1.
A.2 138 Troubleshooting the Code Editor Problem: You cannot see the Output tab in the Project window. Solution: From the View menu select Output. Problem: When building the project, you see this error message: “process_begin: CreateProcess((null), C:\DOCUME~1\bok\LOCALS~1\Temp\make81222.bat, ...) failed make (e=2): The system cannot find the file specified.”. Solution: Rebuild the project, making certain that no other instances of PSoC Designer are building at the same time.
A.3 A.4 Troubleshooting the Debugger Problem: User cannot connect to a pod. Solution: There are a few possible issues that may cause this problem. One way to begin the solution process is to create a decision tree that lists the issue and presents potential causes. Problem: While debugging, you see the message “Invalid Memory Reference.” Solution: Similar to previous solution. Problem: User cannot connect to ICE. Solution: Similar to the previous solution.
A.6 I2C Hot Swapping Problem: The PSoC does not function independently as a hot swap controller with I2C. The protection diodes on the GPIO pins attached to the I2C bus load the bus if the PSoC Vdd is separate from the I2C power supply and is powered down. Solution: We have a workaround fix. Please find attached block in PDF format. Figure 1-2.
A.9 Using an External USB Hub Problem: Use an external USB hub to program your PSoC TWICE as fast. The time it takes to program a PSoC is often reduced when the PSoC is connected to an external USB hub. This is because of the Intel chipset based USB found on many computers. There are three common USB hub systems: UHCI, OHCI, and EHCI. UHCI and OHCI were developed for the original USB 1.1 spec. UHCI was designed by Intel and is a bare-bones implementation. OHCI is more aggressive and is more widely used.
A.11 Project Cloning Warnings Problem: You clone a project and receive what seem to be strange errors or warnings. Solution: To convert your project between device types, select Start New Project. Then select Clone a Configuration and type a name for your new project. In the existing configuration window, select the project to clone and the new device type into which to migrate your project. Select Finish.
Problem: You have minibars stacked on the left side of the screen pushing down the viewable screen area. Solution: Increase size of the window and move minibars to the desired location. Then switch to another PSoC Designer state to memorize the layout of the current state. Repeat this process for the Chip-Level Editor, the Code Editor, and the Debugger because PSoC Designer memorizes their layouts independently.
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Appendix B. Build Process This appendix describes the build utilities and process and provides examples for PSoC Designer. B.1 Build Utilities The build utilities are single-purpose applications that contribute to the build process. Table B-1 presents a list of these utilities. These utilities/programs are installed in the Tools folder beneath the root installation of PSoC Designer. Table B-1. Utilities and Programs Utility/Program iasm8c.exe iccomm8c.exe iccm8c.exe ilinkm8c.exe ilstm8c.exe icppw.
B.2 Make Process B.2.1 Environment Variables PATH: Change the path to add the PSoC designer tools directory. Example: PATH=c:\program files\cypress microsystems\psoc designer\tools;%PATH% DEVICE: The name of the device. Example: DEVICE=CY8C24794 BASEDEVICE: The tools/include subdirectory of the PSoC Designer install directory that contains the include files for the DEVICE. Example: BASEDEVICE=CY8C24090 LASTROM: The last location in ROM. Example: LASTROM=0x3fff B.2.
B.2.3.2 project.mk Project.mk is generated by psocmakemake.exe from environment variables and the project’s .soc file. It is rewritten by the PSoC Designer build process. This section describes what these symbolic variables are and gives examples of what values they can have. Figure B-1 shows an example of a project.mk file for the c24 project using a CY8C24423 device. Figure B-1. Example PROJECT.
master make file also statically adds an include paths to ./lib and %PSOCDIR%/tools/include. However, assume a project had a local.mk file that wanted to add additional include paths to common folders that where located away from the project folder using a statement like: INCLUDE_PATH:=$(INCLUDE_PATH);../common The assignment, in the master make file, to CY_INCLUDE_PATH receives the potential list of include folders.
CODECOMPRESSOR – This is used by the linker in the master make file. PSoC Designer’s Project > Settings Compiler GUI shows two options for the Code Compression Technologies: (1) Condensation and (2) Sublimation. These GUI options are only shown for non-RAM-paged device projects.
B.2.3.3 Local.mk This file contains additional make instructions. It is not touched by the make process. Here you can add and/or modify the build variables set in project.mk. B.2.3.4 project.dep Created by the ‘mkdepend’ via the make depend command. This file contains the include dependencies for the project. It is rewritten by the build process. B.2.3.5 local.dep This file contains additional file dependencies and make commands. It is not touched by the make process.
B.4 Examples B.4.1 Batch Build File This is a .bat file that builds a project; here PSoC Designer is installed in c:\a\pd set PSOCTOOLS=c:\a\pd\tools set PATH=%PSOCTOOLS%;c:\winnt\system32;c:\winnt set DEVICE=CY8C24423B set BASEDEVICE=CY8C24000B set LASTROM=0xFFF make -f %PSOCTOOLS%\Makefile clean make PROJNAME=aa -f %PSOCTOOLS%\Makefile makemake make –f %PSOCTOOLS%\Makefile depend make -f %PSOCTOOLS%\Makefile B.4.
B.4.3 Add External Files to the Project This is a trick for local.mk to have a ‘custom’ rule to build/add files outside of the project folder. # CSRCS is used by makedepends to get the external headers/dependencies CSRCS:=$(CSRCS) ../common/foo.c OBJECT_SOURCES:=$(OBJECT_SOURCES) foo.c # new rule to tell MAKE to get C files from ../common # DON'T have files in COMMON with the same name as this project's Source # Files because we won't know which file MAKE will build last. obj/%.o : ../common/%.
Glossary A) active windows Subsystem-related windows that are open and workable. analog PSoC blocks Basic programmable opamp circuits. There are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
Glossary design (export/ import) One or more loadable configurations that can be exported from a project then imported and used in a new or existing project. A loadable configuration consists of one or more “placed” user modules with module parameters, Global Resources, set pinouts, and generated application files. design browser Venue to identify reusable designs for import to PSoC Designer projects. Chip-Level Editor PSoC Designer subsystem where you choose/configure your device.
Glossary miniProg1 Developmental programmer that provides a low-cost solution for learning about, programming and evaluating the PSoC. P pod Part of the ICE that emulates functionality, in which debugging occurs. PSoC Cypress MicroSystems’ Programmable System-on-Chip (PSoC) mixed signal array. PSoC™ and Programmable System-on-Chip™ are trademarks of Cypress MicroSystems, Inc. PSoCEval1 Evaluation board that provides a low-cost solution for learning about, programming, and evaluating the PSoC.
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Index A address spaces 96 addressing modes 96 analog input connection 38 analog section, manually turning off troubleshooting 140 application editor adding existing files 93 adding new files 93 additional generated files 90 file definitions and recommendations 87 modifying files 92 removing files 93 searching files 94 troubleshooting 138 working in 92 application files, generating 46 application programming interfaces 48 AreaName not defined, troubleshooting 142 assembler accessing 95 address spaces 96 add
Copyrights troubleshooting 139 typical event uses 121 watch variables 119 default input connection 38 design rule checker 45 running 45 development kit 109 device editor interrupt vectors 50 troubleshooting 137 digital interconnect row input window 34 dynamic event points 120 dynamic reconfiguration add configurations 52 application editor 55 code generation 55 delete configurations 53 global parameters 54 port pin settings 54 rename configurations 54 E event examples find memory write 122 register A valu
I I2C hot swapping, troubleshooting 140 ICE connecting to PC 112 troubleshooting 139 ICE, connecting to 112 icons generate application 46 interconnect view 27 next allowed placement 20 options for modifying files 92 place user module 20 restore default pinout 37 undo place user module 20 incorrect code compilation, troubleshooting 139 instruction format 96 instruction set notation 99 interconnections analog clock select 29 analog column clock 29 analog column input mux 30 analog column input select 30 analo
Copyrights make process 146 make utility 99 menu options in the debugger 111 microprocessor (MCU) 95 N name user modules 20 O obj (objects) file folder 88 options for modifying source files 92 output file folder 88 output tab 89 P parameters, user modules 21 parts catalog 18 pinout specification 37 placing user modules 19–?? POD detection, troubleshooting 141 port connections analog input 38 analog output buffer 38 default input 38 Ext Ref 41 ExternalGND 41 Global_IN_x 39 Global_OUT_x 39 I2C SDA 42 StdC
internal 95 removing user modules 21 rename user modules 20 resource manager 19 resource meter 44 rotating user modules 21 row logic table input 35 row logic table select 36 S shadow registers 90 source files folder 89 source files generated by generate application operation 47 source tree 89 stack overflow, event examples 122 system interface 88 system supervisor call 133 T trace issues, troubleshooting 140 trace window 116 tracking device space 44 troubleshooting analog section, manually turning off 140
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