Datasheet

PSoC Designer IDE Guide, Document # 001-42655 Rev *B 27
Chip-Level Editor
Designer. A complete discussion of the relation of the sleep and watchdog timers is in the PSoC
Technical Reference Manual.
2.4 Project Backup Folder
PSoC Designer maintains a backup folder in the project directory for files that were removed from
the source tree. This includes files that are manually removed and files removed due to cloning or
code generation. The backup folder only retains the version of the file that was last removed. The
files are named identically to the original project file and the \lib directory is not retained (i.e.,
library files are placed directly under the backup folder).
2.5 Specifying Interconnects
Interconnectivity allows communication between user modules, PSoC blocks, pins, and other on-
chip resources.
Connections are shown as lines between elements, special symbols, or flag connectors. Flag con-
nectors are used when the connection is made to a point where drawing a line results in a cluttered
display, with the legend indicating the origin of the connection. Connections to pins are shown as
lines from interconnection buses. The interconnection bus structure depends on the PSoC device
selected and can consist of one or more levels of buses between the digital PSoC blocks and the
pins.
Connections between analog PSoC blocks and pins are made through the analog input muxes and
output buses.
Pin names are duplicated in several places, since they are multifunctional, and are highlighted when
used with lines showing their current connection state. The location of the pin to which a line is
drawn indicates the usage of the pin. Lines drawn to the pins on the left edge indicate that the pins
are used as inputs, while the right edge indicates the pins are used as output.
Pins in the upper groups indicate connection to the digital network, while lower groups indicate ana-
log connections. Lines drawn from multiple locations on the same pin indicate that the shown combi-
nation is electrically valid.
To specify interconnections, click the Interconnect folder in the Workspace Explorer.
User module interconnections consist of connections to surrounding PSoC blocks, output bus, input
bus, internal system clocks and references, external pins, and analog output buffers. Multiplexers
may also be configured to route signals throughout the PSoC block architecture.
Digital PSoC blocks are connected through the Global_IN and Global_OUT buses to external pins
and to other digital PSoC blocks. There are eight Global_IN and eight Global_OUT bus lines, num-
bered 0 through 7. For external pin connections, the number of the Global bus line corresponds to
the bit number of the associated port. For example, Global_IN_0 can connect to pins associated with
P0[0], P1[0], P2[0], etc. The Global_OUT buses can drive the inputs to other digital PSoC blocks.
However, all Global_OUT lines do not reach all digital PSoC blocks. Refer to the PSoC Technical
Reference Manual for details on the global bus interconnections.
When setting output parameters to the Global_OUT lines, only one PSoC block drives a single
Global_OUT line at a time. Global_OUT lines used by a user module are not available to other user
modules for output. For example, if two timer user modules are placed and the first timer is set to use
Global_OUT_1 for output, attempting to set the output for the second timer to Global_OUT_1 fails.