Datasheet
PSoC Designer IDE Guide, Document # 001-42655 Rev *B 45
Chip-Level Editor
The resource meter tracks Analog Blocks, Digital Blocks, RAM, ROM, and the use of device specific
special resources such as the decimator, CapSense™ blocks, or I
2
C controller. As you place user
modules, you can view how many analog and digital PSoC blocks you have available and how many
you have used. RAM and ROM monitors track the amount RAM and ROM required to employ each
selected user module.
Figure 2-37. PSoC Block Resource Meter
2.8 Design Rule Checker
The Design Rule Checker (DRC) operates on a collection of predetermined rules associated with
elements in a project database. Once started, the DRC runs and then communicates the results of a
“rule” evaluation.
The DRC is designed to point out potential errors or rule violations in your project that might eventu-
ally pose problems. The DRC does not impose limitations or prevent you from proceeding with your
project “as is.” It simply notifies you of PSoC user module, software, and hardware elements you
may not be aware of when configuring and sourcing your device. It is an additional tool to provide
support for user-configuration.
The PSoC Designer collection of rules is being updated on an ongoing basis. A few sample DRC
rules include:
A project uses a Phase Locked Loop (PLL) but has not been configured with an External Crystal
The device is set to 24 MHz and 3V operation
The device is set to 48 MHz and 3V for Digital Clock Operation
Failure to set required parameters or connections
P0[1] and P0[0] Pins not High-Z with External Crystal
3.3V Indicating ICE is 5V Supply Only
Global Bus with Signal Pulse Width < 1/12 MHz
Phase Consistency Between Output to Input of SC blocks
PWM/Counter/Timer with Pulse Width > Period
Inappropriate Ground and Reference Level Selections
To run the Design Rule Checker, go to: Tools > Design Rule Checker.
In a matter of seconds, you can review the results of the rule evaluation in the Results tab of the Out-
put Status window.