Datasheet

PSoC Designer IDE Guide, Document # 001-42655 Rev *B 73
System-Level Editor
When the hex file generation is complete, PSoC Designer compiles the design and programming
information into a set of custom reports, and then presents the information on the BOM/Schematic
desktop.
Figure 3-9. BOM/Schematic Desktop
.
The BOM Schematic desktop shows the resulting pin assignments on the device. The desktop also
includes hypertext links to the BOM, data sheet, and schematic custom created for your design.
Click on any hyperlink to view the output in a separate window.
3.11 Developing Complex Designs
The pin assignment process is straight forward with what seems like little complexity. This is by
design. PSoC Designer is a tool that removes the complexity from the chip programming process.
There are times however, when preparing a complex design, that conflicts arise. At the end of the
process you find that you cannot assign a value to a specific pin because PSoC Designer, as a part
of the build process, assigned a different value.
This section provides information to help you understand the processes that create those assign-
ments and what you can do with your design to make the results error and conflict free.
3.11.1 Preparing Your Design
To illustrate the design process, this section takes you through the entire design process. The exam-
ple is designed to cause pin assignment conflicts, so you can see the process of eliminating them.
This example uses:
 Two Watchdog timers (WDG)
 Two PWMs
 One voltage input
 One I2C Slave
 One Generic pin
 One interface