Datasheet

96 PSoC Designer IDE Guide, Document # 001-42655 Rev *B

Assembler

5.2.1 Address Spaces

There are three separate address spaces implemented in the Assembler:

■ Register Space (REG) – Accessed through the MOV and LOGICAL instructions. There are 8

address bits available to access the register space, plus an extended address bit via the Flag

■ Data RAM Space – Contains the data/program stack and space for variable storage. All the read

and write instructions, as well as instructions which operate on the stacks, use data RAM space.

Data RAM addresses are 8 bits wide.

The M8C is able to directly access 256 bytes of RAM. Some PSoC devices have more than a

256-byte RAM page. These devices access multiple RAM pages using a combination of page

mode bits in the Flag and Paging registers of the register address space. See the PSoC device

data sheets and the PSoC Technical Reference Manual for details.

■ Program Memory Space – Organized into 256 byte pages, such that the PCH register contains

the memory page number and the PCL register contains the offset into that memory page. The

M8C automatically advances PCH when it needs to cross a page boundary. The user need not

be concerned with program memory page boundaries, because they are invisible within the pro-

gramming module. The one exception to this is that non-jump instructions ending on a page

boundary take an extra cycle to complete. Jump instructions are not affected in this manner.

5.2.2 Instruction Format

Instruction addressing is divided into two groups:

■ Logic, Arithmetic, and Data Movement Functions (Unconditional) –

These are 1-, 2-, or 3-byte instructions. The first byte of the instruction contains the opcode for

that instruction. In 2-byte instructions, the second byte contains either a data value or an address.

■ Jump and Call Instructions, including INDEX (Conditional) –

Most jumps, plus CALL and INDEX, are 2-byte instructions. The opcode is contained in the upper

4 bits of the first instruction byte and the destination address is stored in the remaining 12 bits.

For program memory sizes larger than 4 KB, a 3-byte format is used.

5.2.3 Addressing Modes

Ten addressing modes are supported. For examples of each see the PSoC Designer Assembly Lan-

guage User Guide.

■ Source Immediate

■ Source Direct

■ Source Indexed

■ Destination Direct

■ Destination Indexed

■ Destination Direct Immediate

■ Destination Indexed Immediate

■ Destination Direct Direct

■ Source Indirect Post Increment

■ Destination Indirect Post Increment