Specifications

CY8C24894
Automotive PSoC
®
Programmable System-on-Chip™
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-53754 Rev. *F Revised July 23, 2013
Features
Automotive Electronics Council (AEC) qualified
Powerful Harvard-architecture processor
M8C processor speeds up to 24 MHz
Two 8 × 8 multiply, 32-bit accumulate
Low power at high speed
Operating voltage: 3.0 V to 5.25 V
Automotive temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC
®
blocks)
Six rail-to-rail analog PSoC blocks provide:
Up to 14-bit analog-to-digital converters (ADCs)
Up to 9-bit digital-to-analog converters (DACs)
Programmable gain amplifiers (PGAs)
Programmable filters and comparators
Four digital PSoC blocks provide:
8- to 32-bit timers, counters, and pulse-width modulators
(PWMs)
Cyclic redundancy check (CRC) and pseudo-random
sequence (PRS) modules
Full- or half-duplex UART
SPI master or slave
Connectable to all general purpose I/O (GPIO) pins
Complex peripherals by combining blocks
Capacitive sensing application capability
Flexible on-chip memory
16 KB flash program storage, 1000 erase/write cycles
1 KB SRAM data storage
In-system serial programming (ISSP)
Partial flash updates
Flexible protection modes
EEPROM emulation in flash
Programmable pin configurations
25 mA sink, 10 mA drive on all GPIOs
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
Up to 47 analog inputs on GPIOs
Two 30 mA analog outputs on GPIOs
Configurable interrupt on all GPIOs
Precision, programmable clocking
Internal ±4% 24/48 MHz oscillator
Internal low-speed, low-power oscillator for watchdog and
sleep functionality
Optional external oscillator, up to 24 MHz
Additional system resources
I
2
C™ slave, master, or multimaster operation up to 400 kHz
Watchdog and sleep timers
User-configurable LVD
Integrated supervisory circuit
On-chip precision voltage reference
Complete development tools
Free development software (PSoC Designer™)
Full-featured in-circuit emulator (ICE) and programmer
Full-speed emulation
Complex breakpoint structure
128 KB trace memory
Logic Block Diagram
Input
Analog
Muxing
DIGITAL SYSTEM
SRAM
1K
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM Flash 16K
Digital
Block
Array
Digital
Clocks
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref.
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
Analog
Block
Array
Internal
Voltage
Ref.
POR and LVD
System Resets
2
MACs
Decimator
Type 2
I2C
Port 7
S
y
s
t
e
m
B
u
s
Errata: For information on silicon errata, see “Errata” on page 46. Details include trigger conditions, devices affected, and proposed workaround.

Summary of content (50 pages)