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ManualsBrandsCYPRESS SEMICONDUCTOR ManualsMicrocontrollers, Microprocessors & QuartzesPSoC® Microcontroller SSOP 48

CY8C29466, CY8C29566

CY8C29666, CY8C29866

Document Number: 38-12013 Rev. *M Page 18 of 47

Table 11-1. Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT0DR 00 RW DBB20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW

PRT0IE 01 RW DBB20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW

PRT0GS 02 RW DBB20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW

PRT0DM2 03 RW DBB20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW

PRT1DR 04 RW DBB21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW

PRT1IE 05 RW DBB21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW

PRT1GS 06 RW DBB21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW

PRT1DM2 07 RW DBB21CR0 47 # ASD11CR3 87 RW C7

PRT2DR 08 RW DCB22DR0 48 # ASC12CR0 88 RW RDI3RI C8 RW

PRT2IE 09 RW DCB22DR1 49 W ASC12CR1 89 RW RDI3SYN C9 RW

PRT2GS 0A RW DCB22DR2 4A RW ASC12CR2 8A RW RDI3IS CA RW

PRT2DM2 0B RW DCB22CR0 4B # ASC12CR3 8B RW RDI3LT0 CB RW

PRT3DR 0C RW DCB23DR0 4C # ASD13CR0 8C RW RDI3LT1 CC RW

PRT3IE 0D RW DCB23DR1 4D W ASD13CR1 8D RW RDI3RO0 CD RW

PRT3GS 0E RW DCB23DR2 4E RW ASD13CR2 8E RW RDI3RO1 CE RW

PRT3DM2 0F RW DCB23CR0 4F # ASD13CR3 8F RW CF

PRT4DR 10 RW DBB30DR0 50 # ASD20CR0 90 RW CUR_PP D0 RW

PRT4IE 11 RW DBB30DR1 51 W ASD20CR1 91 RW STK_PP D1 RW

PRT4GS 12 RW DBB30DR2 52 RW ASD20CR2 92 RW D2

PRT4DM2 13 RW DBB30CR0 53 # ASD20CR3 93 RW IDX_PP D3 RW

PRT5DR 14 RW DBB31DR0 54 # ASC21CR0 94 RW MVR_PP D4 RW

PRT5IE 15 RW DBB31DR1 55 W ASC21CR1 95 RW MVW_PP D5 RW

PRT5GS 16 RW DBB31DR2 56 RW ASC21CR2 96 RW I2C_CFG D6 RW

PRT5DM2 17 RW DBB31CR0 57 # ASC21CR3 97 RW I2C_SCR D7 #

PRT6DR 18 RW DCB32DR0 58 # ASD22CR0 98 RW I2C_DR D8 RW

PRT6IE 19 RW DCB32DR1 59 W ASD22CR1 99 RW I2C_MSCR D9 #

PRT6GS 1A RW DCB32DR2 5A RW ASD22CR2 9A RW INT_CLR0 DA RW

PRT6DM2 1B RW DCB32CR0 5B # ASD22CR3 9B RW INT_CLR1 DB RW

PRT7DR 1C RW DCB33DR0 5C # ASC23CR0 9C RW INT_CLR2 DC RW

PRT7IE 1D RW DCB33DR1 5D W ASC23CR1 9D RW INT_CLR3 DD RW

PRT7GS 1E RW DCB33DR2 5E RW ASC23CR2 9E RW INT_MSK3 DE RW

PRT7DM2 1F RW DCB33CR0 5F # ASC23CR3 9F RW INT_MSK2 DF RW

DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW

DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW

DBB00DR2 22 RW 62 A2 INT_VC E2 RC

DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W

DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC

DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC

DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW

DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW

DCB02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W

DCB02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W

DCB02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R

DCB02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R

DCB03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW

DCB03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW

DCB03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW

DCB03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW

DBB10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0

DBB10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1

DBB10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2

DBB10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3

DBB11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4

DBB11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5

DBB11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6

DBB11CR0 37 # ACB01CR2 77 RW B7 CPU_F F7 RL

DCB12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8

DCB12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9

DCB12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA

DCB12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB

DCB13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FC

DCB13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FD

DCB13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #

DCB13CR0 3F # ACB03CR2 7F RW BF CPU_SCR0 FF #

Blank fields are Reserved and should not be accessed. # Access is bit specific.

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