User manual

CY8C29466, CY8C29566
CY8C29666, CY8C29866
Document Number: 38-12013 Rev. *M Page 30 of 47
Figure 12-4. PLL Lock Timing Diagram
Figure 12-5. PLL Lock for Low Gain Setting Timing Diagram
Figure 12-6. External Crystal Oscillator Startup Timing Diagram
Figure 12-7. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 12-8. 32 kHz Period Jitter (ECO) Timing Diagram
DC
ILO
Internal Low Speed Oscillator Duty Cycle 20 50 80 %
Step24M 24 MHz Trim Step Size – 50 – kHz
Fout48M 48 MHz Output Frequency 46.8 48.0 49.2
[9, 11]
MHz Trimmed. Using factory trim
values.
Jitter24M1 24 MHz Period Jitter (IMO) – 600 – ps
F
MAX
Maximum frequency of signal on row input or row
output.
– – 12.3 MHz
SR
POWER_UP
Power Supply Slew Rate – – 250 V/ms Vdd slew rate during power up.
T
POWERUP
Time from end of POR to CPU executing code – 16 100 ms Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual.
Table 12-17. AC Chip-Level Specifications (continued)
Symbol Description Min Typ Max Units Notes
24 MHz
F
PLL
PLL
Enable
T
PLLSLEW
PLL
Gain
0
24 MHz
F
PLL
PLL
Enable
T
PLLSLEWLOW
PLL
Gain
1
32 kHz
F
32K2
32K
Select
T
OS
Jitter24M1
F
24M
Jitter32k
F
32K2
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