User`s guide

CYV15G0404DXB Evaluation Board
Users Guide
Page 7 of 56
Figure 4-2 shows the transmitter section of CYV15G0404DXB in more detail. The building blocks of the channel include the
phase-align buffer, the 8B/10B encoder and the serializer (shifter). When the reclocker function is enabled, the recovered serial
data is reclocked and retransmitted through the serial outputs.
Figure 4-2. Transmit Path Block Diagram
Shifter
TXLBA
Transmit Path Block Diagram
Input
Register
Phase-Align
Buffer
Encoder
BIST LFSR
SPDSELA
TXCLKA
Bit-Rate Clock
Character-Rate Clock A
OUTA1+
OUTA1-
OUTA2+
OUTA2-
8
Input
Register
Phase-Align
Buffer
8B/10B
BIST LFSR
Transmit PLL
Clock Multiplier A
TXCTA[1:0]
OE[2..1]A
TXBIST
ENCBYPA
TXCKSELA
= Internal Signal
TXERRA
TXCLKOA
TXDA[7:0]
2
10
10
10
10
A
PABRSTA
OE[2..1]A
10
RCLK[A..D] are Internal Reclocker Character Clock Signals
Encoder
RED[A..D] are Internal Reclocker Serial Data Signals
TXRATEA
RCLKENA
RCLKA
0
1
Register
REDA
RCLKENA
0
1
TXLB[A..D] are Internal Serial Loopback Signals
REFCLKA+
REFCLKA-
Shifter
TXLBB
Input
Register
Phase-Align
Buffer
Encoder
BIST LFSR
SPDSELB
TXCLKB
Bit-Rate Clock
Character-Rate Clock B
OUTB1+
OUTB1-
OUTB2+
OUTB2-
8
Input
Register
Phase-Align
Buffer
8B/10B
BIST LFSR
Transmit PLL
Clock Multiplier B
TXCTB[1:0]
OE[2..1]B
TXBIST
ENCBYPB
TXCKSELB
TXERRB
TXCLKOB
TXDB[7:0]
2
10
10
10
10
B
PABRSTB
OE[2..1]B
10
Encoder
TXRATEB
RCLKENB
RCLKB
0
1
Register
REDB
RCLKENB
0
1
REFCLKB+
REFCLKB-
Shifter
TXLBC
Input
Register
Phase-Align
Buffer
Encoder
BIST LFSR
SPDSELC
TXCLKC
Bit-Rate Clock
Character-Rate Clock C
OUTC1+
OUTC1-
OUTC2+
OUTC2-
8
Input
Register
Phase-Align
Buffer
8B/10B
BIST LFSR
Transmit PLL
Clock Multiplier C
TXCTC[1:0]
OE[2..1]C
TXBIST
ENCBYPC
TXCKSELC
TXERRC
TXCLKOC
TXDC[7:0]
2
10
10
10
10
C
PABRSTC
OE[2..1]C
10
Encoder
TXRATEC
RCLKENC
RCLKB
0
1
Register
REDC
RCLKENC
0
1
REFCLKC+
REFCLKC-
Shifter
TXLBD
Input
Register
Phase-Align
Buffer
Encoder
BIST LFSR
SPDSELD
TXCLKD
Bit-Rate Clock
Character-Rate Clock D
OUTD1+
OUTD1-
OUTD2+
OUTD2-
8
Input
Register
Phase-Align
Buffer
8B/10B
BIST LFSR
Transmit PLL
Clock Multiplier D
TXCTD[1:0]
OE[2..1]D
TXBIST
ENCBYPD
TXCKSELD
TXERRD
TXCLKOD
TXDD[7:0]
2
10
10
10
10
D
PABRSTD
OE[2..1]D
10
Encoder
TXRATED
RCLKEND
RCLKD
0
1
Register
REDD
RCLKEND
0
1
REFCLKD+
REFCLKD-
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