Datasheet

ManualsBrandsCypress Semiconductor ManualsComputer equipmentFX2LP

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

EZ-USB

FX2LP™ USB Microcontroller

High-Speed USB Peripheral Controller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-08032 Rev. *V Revised February 7, 2012

EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller

Features

■ USB 2.0 USB IF high speed certified (TID # 40460272)

■ Single chip integrated USB 2.0 transceiver, smart SIE, and

enhanced 8051 microprocessor

■ Fit, form, and function compatible with the FX2

❐ Pin compatible

❐ Object code compatible

❐ Functionally compatible (FX2LP is a superset)

■ Ultra low power: I

No more than 85 mA in any mode

❐ Ideal for bus and battery powered applications

■ Software: 8051 code runs from:

❐ Internal RAM, which is downloaded through USB

❐ Internal RAM, which is loaded from EEPROM

❐ External memory device (128 pin package)

■ 16 KB of on-chip code/data RAM

■ Four programmable BULK, INTERRUPT, and

ISOCHRONOUS endpoints

❐ Buffering options: Double, triple, and quad

■ Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

■ 8-bit or 16-bit external data interface

■ Smart media standard ECC generation

■ GPIF (general programmable interface)

❐ Enables direct connection to most parallel interfaces

❐ Programmable waveform descriptors and configuration

registers to define waveforms

❐ Supports multiple ready (RDY) inputs and Control (CTL)

outputs

■ Integrated, industry standard enhanced 8051

❐ 48 MHz, 24 MHz, or 12 MHz CPU operation

❐ Four clocks per instruction cycle

❐ Two USARTs

❐ Three counter/timers

❐ Expanded interrupt system

❐ Two data pointers

■ 3.3 V operation with 5 V tolerant inputs

■ Vectored USB interrupts and GPIF/FIFO interrupts

■ Separate data buffers for the setup and data portions of a

CONTROL transfer

■ Integrated I

C controller, runs at 100 or 400 kHz

■ Four integrated FIFOs

❐ Integrated glue logic and FIFOs lower system cost

❐ Automatic conversion to and from 16-bit buses

❐ Master or slave operation

❐ Uses external clock or asynchronous strobes

❐ Easy interface to ASIC and DSP ICs

■ Available in commercial and industrial temperature grade

(all packages except VFBGA)

Features (CY7C68013A/14A only)

■ CY7C68014A: Ideal for Battery Powered Applications

❐ Suspend current: 100 A (typ)

■ CY7C68013A: Ideal for Non Battery Powered Applications

❐ Suspend current: 300 A (typ)

■ Available in Five Pb-free Packages with Up to 40 GPIOs

❐ 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin

QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin

VFBGA (24 GPIOs)

Features (CY7C68015A/16A only)

■ CY7C68016A: Ideal for Battery Powered Applications

❐ Suspend current: 100 A (typ)

■ CY7C68015A: Ideal for Non Battery Powered Applications

❐ Suspend current: 300 A (typ)

■ Available in Pb-free 56-pin QFN Package (26 GPIOs)

■ Two more GPIOs than CY7C68013A/14A enabling additional

features in same footprint

Summary of content (66 pages)

PAGE 1
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EZ-USB® FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller Features ■ USB 2.0 USB IF high speed certified (TID # 40460272) ■ 3.3 V operation with 5 V tolerant inputs ■ Single chip integrated USB 2.
PAGE 2
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Logic Block Diagram High performance micro using standard tools with lower-power options 24 MHz Ext. XTAL /0.5 /1.0 /2.0 I2C 8051 Core 12/24/48 MHz, four clocks/cycle Address (16) / Data Bus (8) x20 PLL VCC Data (8) Address (16) FX2LP 1.5k connected for full speed D+ D– USB 2.0 XCVR Integrated full speed and high speed XCVR CY Smart USB 1.1/2.
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Contents Applications ...................................................................... 4 Functional Overview ........................................................ 4 USB Signaling Speed .................................................. 4 8051 Microprocessor ................................................... 4 I2C Bus ........................................................................ 4 Buses .......................................................
PAGE 4
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1. Applications Figure 2-1. Crystal Configuration ■ Portable video recorder ■ MPEG/TV conversion ■ DSL modems ■ ATA interface ■ Memory card readers ■ Legacy conversion devices ■ Cameras ■ Scanners ■ Wireless LAN ■ MP3 players The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz. ■ Networking 2.2.
PAGE 5
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 1.
PAGE 6
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A The FX2LP jump instruction is encoded as follows: Table 3.
PAGE 7
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 4.
PAGE 8
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2-2. Reset Timing Plots RESET# RESET# VIL VIL 3.3V 3.0V 3.3V VCC VCC 0V 0V TRESET TRESET Power on Reset Powered Reset Table 2-1. Reset Timing Values 2.10 Program/Data RAM Condition TRESET Power on reset with crystal 5 ms Power on reset with external clock 200 s + Clock stability time Powered Reset 200 s 2.10.
PAGE 9
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2-3. Internal Code Memory, EA = 0 Inside FX2LP Outside FX2LP FFFF 7.5 KBytes USB regs and 4K FIFO buffers (RD#,WR#) E200 E1FF 0.
PAGE 10
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2-4. External Code Memory, EA = 1 Inside FX2LP Outside FX2LP FFFF 7.5 KBytes USB regs and 4K FIFO buffers (RD#,WR#) E200 E1FF 0.
PAGE 11
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.12 Endpoint RAM 2.12.3 Setup Data Buffer 2.12.1 Size A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data from a CONTROL transfer. ■ 3 × 64 bytes (Endpoints 0 and 1) ■ 8 × 512 bytes (Endpoints 2, 4, 6, 8) 2.12.4 Endpoint Configurations (High Speed Mode) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. 2.12.
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.12.5 Default Full Speed Alternate Settings Table 5. Default Full Speed Alternate Settings[4, 5] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) 2.12.
PAGE 13
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.13.3 GPIF and FIFO Clock Rates 2.15 ECC Generation[7] An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked.
PAGE 14
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.18 I2C Controller 2 FX2LP has one I C port that is driven by two internal controllers, one that automatically operates at boot time to load VID/PID/DID and configuration information, and another that the 8051 uses when running to control external I2C devices. The I2C port operates in master mode only. Table 8. Part Number Conversion Table 2.18.1 I2C Port Pins The I2C pins SCL and SDA must have external 2.
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3. Pin Assignments Figure 3-1 on page 16 identifies all signals for the five package types. The following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 128-pin, 100-pin, and 56-pin packages.
PAGE 16
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-1.
PAGE 17
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-2.
PAGE 18
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-3.
PAGE 19
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-4.
PAGE 20
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-5.
PAGE 21
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-6. CY7C68013A 56-pin VFBGA Pin Assignment – Top View 1 2 3 4 5 6 7 8 A 1A 2A 3A 4A 5A 6A 7A 8A B 1B 2B 3B 4B 5B 6B 7B 8B C 1C 2C 3C 4C 5C 6C 7C 8C D 1D 2D 7D 8D E 1E 2E 7E 8E F 1F 2F 3F 4F 5F 6F 7F 8F G 1G 2G 3G 4G 5G 6G 7G 8G H 1H 2H 3H 4H 5H 6H 7H 8H Document #: 38-08032 Rev.
PAGE 22
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.1 CY7C68013A/15A Pin Descriptions The FX2LP pin descriptions follow.[10] Table 10. FX2LP Pin Descriptions 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Description 10 9 10 3 2D AVCC Power N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides power to the analog section of the chip. 17 16 14 7 1D AVCC Power N/A Analog VCC. Connect this pin to 3.3V power source.
PAGE 23
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Description Output L Breakpoint. This pin goes active (HIGH) when the 8051 address bus matches the BPADDRH/L registers and breakpoints are enabled in the BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT register is HIGH, this signal pulses HIGH for eight 12-/24-/48 MHz clocks.
PAGE 24
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Description 85 70 43 36 7F PA3 or WU2 I/O/Z I Multiplexed pin whose function is selected by: (PA3) WAKEUP.7 and OEA.3 PA3 is a bidirectional I/O port pin. WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4).
PAGE 25
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Description 55 45 30 23 5G PB5 or FD[5] I/O/Z I Multiplexed pin whose function is selected by the (PB5) following bits: IFCONFIG[1..0]. PB5 is a bidirectional I/O port pin. FD[5] is the bidirectional FIFO/GPIF data bus. 56 46 31 24 5F PB6 or FD[6] I/O/Z I Multiplexed pin whose function is selected by the (PB6) following bits: IFCONFIG[1..
PAGE 26
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Description 104 82 54 47 6B PD2 or FD[10] I/O/Z I Multiplexed pin whose function is selected by the (PD2) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[10] is the bidirectional FIFO/GPIF data bus. 105 83 55 48 6A PD3 or FD[11] I/O/Z I Multiplexed pin whose function is selected by the (PD3) IFCONFIG[1..0] and EPxFIFOCFG.
PAGE 27
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Description 112 90 – – – PE4 or RXD1OUT I/O/Z I Multiplexed pin whose function is selected by the (PE4) PORTECFG.4 bit. PE4 is a bidirectional I/O port pin. RXD1OUT is an active-HIGH output from 8051 UART1. When RXD1OUT is selected and UART1 is in Mode 0, this pin provides the output data for UART1 only when it is in sync mode.
PAGE 28
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA Name Type Default Description 70 55 37 30 7G CTL1 or FLAGB O/Z H Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL1 is a GPIF control output. FLAGB is a programmable slave-FIFO output status flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
PAGE 29
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 TQFP TQFP SSOP QFN VFBGA 50 Default Description TXD0 Output H TXD0 is the active-HIGH TXD0 output from 8051 UART0, which provides the output clock in sync mode, and the output data in async mode. – – – – CS# Output H CS# is the active-LOW chip select for external memory. 41 32 – – – WR# Output H WR# is the active-LOW write strobe output for external memory.
PAGE 30
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 4. Register Summary FX2LP register bit definitions are described in the FX2LP TRM in greater detail. Table 11.
PAGE 31
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11. FX2LP Register Summary (continued) Hex E62B E62C E62D E62E E62F E630 H.S. E630 F.S. E631 H.S. E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.S E634 H.S. E634 F.S E635 H.S. E635 F.S E636 H.S. E636 F.S E637 H.S. E637 F.
PAGE 32
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
PAGE 33
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
PAGE 34
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
PAGE 35
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
PAGE 36
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11.
PAGE 37
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 5. Absolute Maximum Ratings 6. Operating Conditions Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. TA (ambient temperature under bias) Commercial .................................................... 0 °C to +70 °C Storage temperature ................................ –65 C to +150 C TA (ambient temperature under bias) Industrial ...................................................
PAGE 38
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 8. DC Characteristics Table 13. DC Characteristics Parameter VCC Description Supply voltage Min Typ Max Unit – Conditions 3.00 3.3 3.60 V VCC Ramp Up 0 to 3.3 V – 200 – – s VIH Input HIGH voltage – 2 – 5.25 V VIL Input LOW voltage – –0.5 – 0.8 V VIH_X Crystal input HIGH voltage – 2 – 5.25 V VIL_X Crystal input LOW voltage – –0.5 – 0.
PAGE 39
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9. AC Electrical Characteristics 9.1 USB Transceiver USB 2.0 compliant in full speed and high speed modes. 9.2 Program Memory Read Figure 9-1. Program Memory Read Timing Diagram tCL CLKOUT[17] tAV tAV A[15..0] tSTBH tSTBL PSEN# [18] tACC1 D[7..0] tDH data in tSOEL OE# tSCSL CS# Table 14. Program Memory Read Parameters Parameter tCL Description 1/CLKOUT Frequency Min Typ Max Unit Notes – 20.83 – ns 48 MHz – 41.66 – ns 24 MHz – 83.
PAGE 40
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.3 Data Memory Read Figure 9-2. Data Memory Read Timing Diagram tCL Stretch = 0 CLKOUT[17] tAV tAV A[15..0] tSTBH tSTBL RD# tSCSL CS# tSOEL OE# [19] tDSU tDH tACC1 D[7..0] data in tCL Stretch = 1 CLKOUT[17] tAV A[15..0] RD# CS# tDSU tACC1[19] D[7..0] tDH data in Table 15. Data Memory Read Parameters Parameter tCL Description 1/CLKOUT frequency Min Typ Max Unit Notes – 20.83 – ns 48 MHz – 41.66 – ns 24 MHz – 83.
PAGE 41
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.4 Data Memory Write Figure 9-3. Data Memory Write Timing Diagram tCL CLKOUT tAV tSTBL tSTBH tAV A[15..0] WR# tSCSL CS# tON1 tOFF1 data out D[7..0] Stretch = 1 tCL CLKOUT tAV A[15..0] WR# CS# tON1 tOFF1 data out D[7..0] Table 16. Data Memory Write Parameters Min Max Unit Notes tAV Parameter Delay from clock to valid address Description 0 10.7 ns – tSTBL Clock to WR pulse LOW 0 11.2 ns – tSTBH Clock to WR pulse HIGH 0 11.
PAGE 42
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.5 PORTC Strobe Feature Timings The RD# and WR# are present in the 100-pin version and the 128-pin package. In these 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from or writes to PORTC. This feature is enabled by setting PORTCSTB bit in CPUCS register. The RD# signal prompts the external logic to prepare the next data byte.
PAGE 43
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.6 GPIF Synchronous Signals Figure 9-6. GPIF Synchronous Signals Timing Diagram[20] tIFCLK IFCLK tSGA GPIFADR[8:0] RDYX tSRY tRYH DATA(input) valid tSGD tDAH CTLX tXCTL DATA(output) N N+1 tXGD Table 17.
PAGE 44
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.1 Slave FIFO Synchronous Read Figure 9-7. Slave FIFO Synchronous Read Timing Diagram[20] tIFCLK IFCLK tSRD tRDH SLRD tXFLG FLAGS DATA N+1 N tOEon tXFD tOEoff SLOE Table 19. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[21] Parameter Description Min Max Typ Min Max Unit tIFCLK IFCLK period 20.83 – – – ns tSRD SLRD to clock setup time 18.
PAGE 45
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 20. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[21] Min Max Unit tIFCLK Parameter IFCLK period Description 20.83 200 ns tSRD SLRD to clock setup time 12.7 – ns tRDH Clock to SLRD hold time 3.7 – ns tOEon SLOE turn on to FIFO data valid – 10.5 ns tOEoff SLOE turn off to FIFO data hold – 10.5 ns tXFLG Clock to FLAGS output propagation delay – 13.
PAGE 46
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.9 Slave FIFO Synchronous Write Figure 9-9. Slave FIFO Synchronous Write Timing Diagram[20] tIFCLK IFCLK SLWR DATA tSWR tWRH N Z tSFD Z tFDH FLAGS tXFLG Table 22. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[21] Min Max Unit tIFCLK Parameter IFCLK period Description 20.83 – ns tSWR SLWR to clock setup time 10.4 – ns tWRH Clock to SLWR hold time 0 – ns tSFD FIFO data to clock setup time 9.
PAGE 47
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.10 Slave FIFO Asynchronous Write Figure 9-10. Slave FIFO Asynchronous Write Timing Diagram[20] tWRpwh SLWR SLWR/SLCS# tWRpwl tSFD tFDH DATA tXFD FLAGS Table 24.
PAGE 48
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A caused the last byte or word to be clocked into the previous auto committed packet. Figure 9-12 shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode. There is no specific timing requirement that should be met for asserting PKTEND pin to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter. The setup time tSPE and the hold time tPEH must be met.
PAGE 49
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.13 Slave FIFO Output Enable Figure 9-14. Slave FIFO Output Enable Timing Diagram[20] SLOE tOEoff tOEon DATA Table 28. Slave FIFO Output Enable Parameters Max Unit tOEon Parameter SLOE assert to FIFO DATA output Description Min 10.5 ns tOEoff SLOE deassert to FIFO DATA hold 10.5 ns 9.14 Slave FIFO Address to Flags/Data Figure 9-15. Slave FIFO Address to Flags/Data Timing Diagram[20] FIFOADR [1.0] tXFLG FLAGS tXFD DATA N N+1 Table 29.
PAGE 50
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.16 Slave FIFO Asynchronous Address Figure 9-17. Slave FIFO Asynchronous Address Timing Diagram[20] SLCS/FIFOADR [1:0] tFAH tSFA SLRD/SLWR/PKTEND Table 31. Slave FIFO Asynchronous Address Parameters[23] Min Max Unit tSFA Parameter FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time Description 10 – ns tFAH RD/WR/PKTEND to FIFOADR[1:0] hold time 10 – ns 9.17 Sequence Diagram 9.17.1 Single and Burst Synchronous Read Example Figure 9-18.
PAGE 51
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ■ Figure 9-18 on page 50 shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read. ■ At t = 0 the FIFO address is stable and the signal SLCS is asserted (SLCS may be tied low in some applications). Note that tSFA has a minimum of 25 ns.
PAGE 52
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 9-20 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the PKTEND pin. ■ At t = 0 the FIFO address is stable and the signal SLCS is asserted. (SLCS may be tied low in some applications) Note that tSFA has a minimum of 25 ns.
PAGE 53
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.17.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 9-21. Slave FIFO Asynchronous Read Sequence and Timing Diagram[20] tSFA tFAH tSFA tFAH FIFOADR t=0 tRDpwl tRDpwh tRDpwl T=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwh SLRD t=2 t=3 T=3 T=2 T=5 T=4 T=6 SLCS tXFLG tXFLG FLAGS tXFD Data (X) Driven DATA tXFD tXFD N N N+3 N+2 tOEon tOEoff tOEon tXFD N+1 tOEoff SLOE t=4 t=1 T=7 T=1 Figure 9-22.
PAGE 54
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.17.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 9-23.
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 10. Ordering Information Table 32.
PAGE 56
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 11. Package Diagrams The FX2LP is available in five packages: ■ 56-pin SSOP ■ 56-pin QFN ■ 100-pin TQFP ■ 128-pin TQFP ■ 56-ball VFBGA Figure 11-1. 56-Pin Shrunk Small Outline Package O56 (51-85062) 51-85062 *E Document #: 38-08032 Rev.
PAGE 57
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-2. 56-Pin QFN 8 × 8 mm Sawn Version (001-53450) 001-53450 *B Document #: 38-08032 Rev.
PAGE 58
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A100RA (51-85050) 51-85050 *D Document #: 38-08032 Rev.
PAGE 59
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-4. 128-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128 (51-85101) 51-85101 *E Document #: 38-08032 Rev.
PAGE 60
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-5. 56-Pin VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901) 001-03901 *E Document #: 38-08032 Rev.
PAGE 61
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 12. PCB Layout Recommendations Follow these recommendations to ensure reliable high performance operation:[25] ■ Bypass and flyback caps on VBus, near connector, are recommended. ■ Four layer impedance controlled boards are required to maintain signal quality. ■ ■ Specify impedance targets (ask your board vendor what they can achieve).
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 13. Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. Design a Copper (Cu) fill in the PCB as a thermal pad under the package.
PAGE 63
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Acronyms Document Conventions Acronyms Used in this Document Units of Measure Acronym Description Symbol Unit of Measure ASIC application specific integrated circuit KHz kilohertz ATA advanced technology attachment mA milliamperes DID device identifier Mbps megabits per second DSL digital service line MBPs megabytes per second DSP digital signal processor MHz megahertz ECC error correction code uA microamperes EEPROM electricall
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document History Page Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB® FX2LP™ USB Microcontroller HighSpeed USB Peripheral Controller Document Number: 38-08032 Orig. of Submission Rev. ECN No.
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB® FX2LP™ USB Microcontroller HighSpeed USB Peripheral Controller Document Number: 38-08032 Orig. of Submission Rev. ECN No.
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