Datasheet

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *V Page 49 of 66
9.13 Slave FIFO Output Enable
Figure 9-14. Slave FIFO Output Enable Timing Diagram
[20]
9.14 Slave FIFO Address to Flags/Data
Figure 9-15. Slave FIFO Address to Flags/Data Timing Diagram
[20]
9.15 Slave FIFO Synchronous Address
Figure 9-16. Slave FIFO Synchronous Address Timing Diagram
[20]
Table 28. Slave FIFO Output Enable Parameters
Parameter Description Min Max Unit
t
OEon
SLOE assert to FIFO DATA output 10.5 ns
t
OEoff
SLOE deassert to FIFO DATA hold 10.5 ns
SLOE
DATA
t
OEon
t
OEoff
Table 29. Slave FIFO Address to Flags/Data Parameters
Parameter Description Min Max Unit
t
XFLG
FIFOADR[1:0] to FLAGS output propagation delay – 10.7 ns
t
XFD
FIFOADR[1:0] to FIFODATA output propagation delay – 14.3 ns
FIFOADR [1.0]
DATA
t
XFLG
t
XFD
FLAGS
NN+1
IFCLK
SLCS/FIFOADR [1:0]
t
SFA
t
FAH
Table 30. Slave FIFO Synchronous Address Parameters
[21]
Parameter Description Min Max Unit
t
IFCLK
Interface clock period 20.83 200 ns
t
SFA
FIFOADR[1:0] to clock setup time 25 – ns
t
FAH
Clock to FIFOADR[1:0] hold time 10 – ns