Specifications

ManualsBrandsCypress Semiconductor ManualsComputer equipmentMoBL-USB CY7C68053

CY7C68053

MoBL-USB™ FX2LP18 USB

Microcontroller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document # 001-06120 Rev *J Revised October 28, 2010

1. Features

■ USB 2.0 9 V USB-IF high speed and full speed compliant (TID#

40000188)

■ Single-chip integrated USB 2.0 transceiver, smart SIE, and

enhanced 8051 microprocessor

■ Ideal for mobile applications (cell phone, smart phones, PDAs,

MP3 players)

❐ Ultra low power

❐ Suspend current: 20 µA (typical)

■ Software: 8051 Code runs from:

❐ Internal RAM, which is loaded from EEPROM

■ 16 kBytes of on-chip code/data RAM

■ Four programmable BULK/INTERRUPT/ISOCHRONOUS

endpoints

❐ Buffering options: double, triple, and quad

■ Additional Programmable (BULK/INTERRUPT) 64-Byte

Endpoint

■ 8 or 16-Bit External Data Interface

■ Smart Media Standard ECC Generation

■ GPIF (General Programmable Interface)

❐ Allows direct connection to most parallel interface

❐ Programmable waveform descriptors and configuration

registers to define waveforms

❐ Supports multiple Ready and Control outputs

■ Integrated, Industry Standard Enhanced 8051

❐ 48 MHz, 24 MHz, or 12 MHz CPU operation

❐ Four clocks per instruction cycle

❐ Three counter/timers

❐ Expanded interrupt system

❐ Two data pointers

■ 1.8 V Core Operation

■ 1.8 V to 3.3 V I/O Operation

■ Vectored USB Interrupts and GPIF/FIFO Interrupts

■ Separate Data Buffers for Setup and Data Portions of a

CONTROL Transfer

■ Integrated I

C Controller, runs at 100 or 400 kHz

■ Four Integrated FIFOs

❐ Integrated glue logic and FIFOs lower system cost

❐ Automatic conversion to and from 16-bit buses

❐ Master or slave operation

❐ Uses external clock or asynchronous strobes

❐ Easy interface to ASIC and DSP ICs

■ Available in Industrial Temperature Grade

■ Available in one Pb-free Package with up to 24 GPIOs

❐ 56-pin VFBGA (24 GPIOs)

x20

PLL

/0.5

/1.0

/2.0

8051 Core

12/24/48 MHz,

Four Clocks/Cycle

VCC

1.5K

D+

D–

Address (16) / Data Bus (8)

GPIF

Smart

USB

1.1/2.0

Engine

USB

2.0

XCVR

16 KB

RAM

4 KB

FIFO

Integrated

Full- and High-Speed

XCVR

Additional IOs (24)

CTL (3)

RDY (2)

24 MHz

Ext. XTAL

Enhanced USB Core

Simplifies 8051 Code

“Soft Configuration”

Easy Firmware Changes

FIFO and Endpoint Memory

(Master or Slave Operation)

General

Programmable I/F

Abundant IO

High-performance microprocessor

using standard tools

with lower-power options

Master

Connected for

Full-Speed

ECC

MoBL-USB FX2LP18

To Baseband Processors/

Application Processors/

ASICS/DSPs

8/16

Up to 96 MBytes/sec

Burst Rate

Logic Block Diagram

[+] Feedback

Summary of content (42 pages)

PAGE 1
CY7C68053 MoBL-USB™ FX2LP18 USB Microcontroller 1. Features ■ USB 2.0 9 V USB-IF high speed and full speed compliant (TID# 40000188) ■ Ideal for mobile applications (cell phone, smart phones, PDAs, MP3 players) ❐ Ultra low power ❐ Suspend current: 20 µA (typical) Integrated, Industry Standard Enhanced 8051 ❐ 48 MHz, 24 MHz, or 12 MHz CPU operation ❐ Four clocks per instruction cycle ❐ Three counter/timers ❐ Expanded interrupt system ❐ Two data pointers ■ Single-chip integrated USB 2.
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CY7C68053 Contents Applications ...................................................................... 3 Functional Overview ........................................................ 3 USB Signaling Speed .................................................. 3 8051 Microprocessor ................................................... 3 I2C™ Bus .................................................................... 4 Buses ..........................................................................
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CY7C68053 Cypress Semiconductor Corporation’s MoBL-USB™ FX2LP18 (CY7C68053) is a low voltage (1.8 V) version of the EZ-USB® FX2LP (CY7C68013A), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.
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CY7C68053 Table 1.
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CY7C68053 If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP18 substitutes its INT2VEC byte. Therefore, if the high byte (‘page’) of a jump-table address is preloaded at location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page. Table 2.
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CY7C68053 Figure 2. Reset Timing Plots RESET# RESET# VIL VIL 1.8 V 1.62 V 1.8 V VCC VCC 0V 0V TRESET TRESET Power on Reset 3.9 Reset and Wakeup The reset and wakeup pins are described in detail in this section. 3.9.1 Reset Pin The input pin, RESET#, resets the FX2LP18 when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C68053, the reset period must allow for the stabilization of the crystal and the PLL.
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CY7C68053 ■ CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be pulled to VCC_IO or GND or driven by another chip. ■ RESET#, WAKEUP#. These pins must be pulled to VCC_IO or GND or driven by another chip during suspend. 3.11 Register Addresses Figure 4. Register Address Memory FFFF 4 kBytes EP2-EP8 buffers (8 x 512) Figure 3. FX2LP18 Internal Code Memory FFFF F000 EFFF 7.5 kBytes USB regs and 4K FIFO buffers 2 kBytes RESERVED E800 E7FF E7C0 E7BF E780 E77F E740 E200 E1FF 0.
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CY7C68053 3.12.4 Endpoint Configurations (High Speed Mode) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any one of the 12 configurations shown in the vertical columns of Figure 5. When operating in full speed BULK mode only the first 64 bytes of each buffer are used. For example, in high speed the maximum packet size is 512 bytes, but in full speed it is 64 bytes.
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CY7C68053 3.12.6 Default High Speed Alternate Settings Table 5. Default High Speed Alternate Settings[3, 4] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 512 bulk[5] 64 int 64 int ep1in 0 512 bulk[5] 64 int 64 int ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×) ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×) ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×) ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×) 3.
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CY7C68053 3.14.1 Three Control OUT Signals 3.16 USB Uploads and Downloads The 56-pin package brings out three of these signals, CTL0–CTL2. The 8051 programs the GPIF unit to define the CTL waveforms. CTLx waveform edges can be programmed to make transitions as fast as once per clock cycle (20.8 ns using a 48 MHz clock). The core has the ability to directly edit the data contents of the internal 16-kByte RAM and of the internal 512-byte scratch pad RAM using a vendor-specific command.
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CY7C68053 Table 6. Strap Boot EEPROM Address Lines to These Values Bytes Example EEPROM [8] A2 A1 A0 N/A N/A N/A 16 24AA00 128 24AA01 0 0 0 256 24AA02 0 0 0 4K 24AA32 0 0 1 8K 24AA64 0 0 1 16K 24AA128 0 0 1 program/data. The available RAM spaces are 16 kBytes from 0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051 is reset. I2C interface boot loads only occur after power on reset. 3.18.
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CY7C68053 Figure 7.
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CY7C68053 4.1 CY7C68053 Pin Descriptions Table 7. FX2LP18 Pin Descriptions [9] 56 VFBGA Name Type Default Description 2D AVCC Power N/A Analog VCC. Connect this pin to 3.3 V power source. This signal provides power to the analog section of the chip. Provide an appropriate bulk/bypass capacitance for this supply rail. 1D AVCC Power N/A Analog VCC. Connect this pin to 3.3 V power source. This signal provides power to the analog section of the chip. 2F AGND Ground N/A Analog Ground.
PAGE 14
CY7C68053 Table 7. FX2LP18 Pin Descriptions (continued)[9] 56 VFBGA Name Type Default Description 6F PA4 or FIFOADR0 I/O/Z I (PA4) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA4 is a bidirectional I/O port pin. FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. 8C PA5 or FIFOADR1 I/O/Z I (PA5) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA5 is a bidirectional I/O port pin.
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CY7C68053 Table 7. FX2LP18 Pin Descriptions (continued)[9] 56 VFBGA Name Type Default Description PORT D 8A PD0 or FD[8] I/O/Z I (PD0) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. 7A PD1 or FD[9] I/O/Z I (PD1) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus.
PAGE 16
CY7C68053 Table 7. FX2LP18 Pin Descriptions (continued)[9] 56 VFBGA Name Type Default Description 7B WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Holding WAKEUP asserted inhibits the MoBL-USB® chip from suspending. This pin has programmable polarity (WAKEUP.4). 3F SCL OD Z Clock for the I2C interface. Connect to VCC_IO or VCC with a 2.2K–10K pull up resistor.
PAGE 17
CY7C68053 5. Register Summary FX2LP18 register bit definitions are described in the MoBL-USB FX2LP18 TRM in greater detail. Table 8.
PAGE 18
CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name E62C 1 ECC1B2 E62D 1 ECC2B0 E62E 1 ECC2B1 Description ECC1 Byte 2 address ECC2 Byte 0 address ECC2 Byte 1 address b7 COL5 LINE15 LINE7 b6 COL4 LINE14 LINE6 b5 COL3 LINE13 LINE5 E62F E630 H.S. E630 F.S. E631 H.S. E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.
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CY7C68053 Table 8.
PAGE 20
CY7C68053 Table 8.
PAGE 21
CY7C68053 Table 8.
PAGE 22
CY7C68053 Table 8.
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CY7C68053 Table 8.
PAGE 24
CY7C68053 6. Absolute Maximum Ratings Maximum power dissipation From AVcc Supply ...................................................... 90 mW Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. From I/O supply .......................................................... 36 mW Storage temperature................................... –65°C to +150°C From core supply........................................................
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CY7C68053 Table 9.
PAGE 26
CY7C68053 8 Table 11. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[17] Parameter Description period[18] Min Max 20.83 200 Unit tIFCLK IFCLK tSRY RDYX to clock setup time 2.9 ns ns tRYH Clock to RDYX 3.7 ns tSGD GPIF data to clock setup time 3.2 ns tDAH GPIF data hold time 4.5 tXGD Clock to GPIF data output propagation delay tXCTL Clock to CTLX output propagation delay ns 15 ns 13.06 ns Max Unit 9.3 Slave FIFO Synchronous Read Figure 9.
PAGE 27
CY7C68053 Table 13. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[17] Parameter Description Min Max Unit 200 ns tIFCLK IFCLK period 20.83 tSRD SLRD to clock setup time 12.7 tRDH Clock to SLRD hold time 3.7 tOEon SLOE turn-on to FIFO data valid tOEoff SLOE turn-off to FIFO data hold 10.5 ns tXFLG Clock to FLAGS output propagation delay 13.5 ns tXFD Clock to FIFO data output propagation delay 17.31 ns ns ns 10.5 2.15 ns 9.
PAGE 28
CY7C68053 9.5 Slave FIFO Synchronous Write Figure 11. Slave FIFO Synchronous Write Timing Diagram[16] tIFCLK IFCLK SLWR DATA tSWR tWRH N Z tSFD Z tFDH FLAGS tXFLG Table 15. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[17] Parameter Description Min Max Unit tIFCLK IFCLK period 20.83 ns tSWR SLWR to clock setup time 18.1 ns tWRH Clock to SLWR hold time 0 ns tSFD FIFO data to clock setup time 10.
PAGE 29
CY7C68053 9.6 Slave FIFO Asynchronous Write Figure 12. Slave FIFO Asynchronous Write Timing Diagram[16] tWRpwh SLWR tWRpwl tSFD tFDH DATA tXFD FLAGS Table 17. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[19] Parameter Description Min Max 50 Unit tWRpwl SLWR pulse LOW ns tWRpwh SLWR pulse HIGH 50 ns tSFD SLWR to FIFO data setup time 10 ns tFDH FIFO data to SLWR hold time 10 tXFD SLWR to FLAGS output propagation delay ns 70 ns 9.
PAGE 30
CY7C68053 There is no specific timing requirement to be met for asserting the PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter. The only consideration is that the setup time tSPE and the hold time tPEH must be met. least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet. Figure 14 shows this scenario.
PAGE 31
CY7C68053 9.9 Slave FIFO Output Enable Figure 16. Slave FIFO Output Enable Timing Diagram[16] SLOE tOEoff tOEon DATA Table 21. Slave FIFO Output Enable Parameters Parameter Description tOEon SLOE assert to FIFO data output tOEoff SLOE deassert to FIFO data hold Min Max Unit 10.5 ns 2.15 10.5 ns 9.10 Slave FIFO Address to Flags/Data Figure 17. Slave FIFO Address to Flags/Data Timing Diagram[16] FIFOADR [1.0] tXFLG FLAGS tXFD DATA N N+1 Table 22.
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CY7C68053 9.11 Slave FIFO Synchronous Address Figure 18. Slave FIFO Synchronous Address Timing Diagram[16] IFCLK SLCS/FIFOADR [1:0] tSFA tFAH Table 23. Slave FIFO Synchronous Address Parameters[10] Parameter Description Min Max Unit 20.83 200 ns tIFCLK Interface clock period tSFA FIFOADR[1:0] to clock setup time 25 ns tFAH Clock to FIFOADR[1:0] hold time 10 ns 9.12 Slave FIFO Asynchronous Address Figure 19.
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CY7C68053 9.13 Sequence Diagram Various sequence diagrams and examples are presented in this section. 9.13.1 Single and Burst Synchronous Read Example Figure 20. Slave FIFO Synchronous Read Sequence and Timing Diagram[16] tIFCLK IFCLK tSFA tSFA tFAH tFAH FIFOADR t=0 tSRD T=0 tRDH >= tSRD >= tRDH SLRD t=3 t=2 T=3 T=2 SLCS tXFLG FLAGS tXFD tXFD Data Driven: N DATA N+1 N+1 N+2 N+3 tOEon tOEoff tOEon tXFD tXFD N+4 tOEoff SLOE t=4 t=1 T=4 T=1 Figure 21.
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CY7C68053 9.13.2 Single and Burst Synchronous Write Figure 22. Slave FIFO Synchronous Write Sequence and Timing Diagram[16] tIFCLK IFCLK tSFA tSFA tFAH tFAH FIFOADR t=0 tSWR tWRH >= tWRH >= tSWR T=0 SLWR t=2 T=2 t=3 T=5 SLCS tXFLG tXFLG FLAGS tFDH tSFD tSFD N+1 N DATA t=1 tFDH T=1 tSFD tSFD tFDH N+3 N+2 T=3 tFDH T=4 tSPE tPEH PKTEND Figure 22 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock.
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CY7C68053 9.13.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 23. Slave FIFO Asynchronous Read Sequence and Timing Diagram[16] tSFA tFAH tSFA tFAH FIFOADR t=0 tRDpwl tRDpwh tRDpwl T=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwh SLRD t=2 t=3 T=2 T=3 T=5 T=4 T=6 SLCS tXFLG tXFLG FLAGS tXFD Data (X) Driven DATA tXFD tXFD N N N+1 N+3 N+2 tOEon tOEoff tOEon tXFD tOEoff SLOE t=4 t=1 T=1 T=7 Figure 24.
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CY7C68053 9.13.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 25.
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CY7C68053 10. Ordering Information Table 24 lists the key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 24.
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CY7C68053 11. Package Diagram The FX2LP18 is available in a 56-pin VFBGA package. Figure 26. 56 VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.
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CY7C68053 12. PCB Layout Recommendations The following recommendations must be followed to ensure reliable high performance operation. ■ Bypass or flyback caps on VBus, near connector, are recommended. ■ At least a four-layer impedance controlled board is required to maintain signal quality. ■ DPLUS and DMINUS trace lengths must be kept within 2 mm of each other in length, with preferred length of 20 to 30 mm. ■ Specify impedance targets (ask your board vendor what they can achieve).
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CY7C68053 13. Acronyms 14. Document Conventions Table 25. Acronyms Used in this Document Units of Measure Acronym Description Table 26.
PAGE 41
CY7C68053 Document History Page Document Title: CY7C68053 MoBL-USB™ FX2LP18 USB Microcontroller Document Number: 001-06120 Revision ECN Orig. of Change Submission Date Description of Change ** 430449 OSG 03/03/06 New data sheet *A 434754 OSG 03/24/06 In Section 3.3, stated that SCL and SDA pins can be connected to VCC or VCC_IO Chnged sections 3.5, 3.18.
PAGE 42
CY7C68053 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.