Specifications

CY7C68053
Document # 001-06120 Rev *J Page 16 of 42
7B WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscil-
lator and interrupts the 8051 to allow it to exit the suspend mode. Holding
WAKEUP asserted inhibits the MoBL-USB
®
chip from suspending. This pin
has programmable polarity (WAKEUP.4).
3F SCL OD Z Clock for the I
2
C interface. Connect to V
CC_IO
or V
CC
with a 2.2K–10K pull up
resistor. (An I
2
C peripheral is required.)
3G SDA OD Z Data for the I
2
C interface. Connect to V
CC_IO
or V
CC
with a 2.2K–10K pull up
resistor. (An I
2
C peripheral is required.)
5A V
CC_IO
Power N/A VCC. Connect this pin to 1.8V to 3.3 V power source.
Provide the appropriate bulk and bypass capacitance for this supply rail.
5B V
CC_IO
Power N/A VCC. Connect this pin to 1.8V to 3.3 V power source.
7E V
CC_IO
Power N/A VCC. Connect this pin to 1.8 V to 3.3 V power source.
8E V
CC_IO
Power N/A VCC. Connect this pin to 1.8V to 3.3 V power source.
5C V
CC_D
Power N/A VCC. Connect this pin to 1.8V power source. (Supplies power to internal digital
1.8 V circuits.)
Provide the appropriate bulk and bypass capacitance for this supply rail.
1G V
CC_A
Power N/A VCC. Connect this pin to 1.8V power source. (Supplies power to internal analog
1.8 V circuits.)
1H GND Ground N/A Ground.
2H GND Ground N/A Ground.
4A GND Ground N/A Ground.
4B GND Ground N/A Ground.
4C GND Ground N/A Ground.
7D GND Ground N/A Ground.
8D GND Ground N/A Ground.
Table 7. FX2LP18 Pin Descriptions (continued)
[9]
56 VFBGA Name Type Default Description
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