Specifications

CY7C68053
Document # 001-06120 Rev *J Page 26 of 42
8
9.3 Slave FIFO Synchronous Read
Notes
16. Dashed lines denote signals with programmable polarity.
17. GPIF asynchronous RDY
x
signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK.
18. IFCLK must not exceed 48 MHz.
Table 11. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
[17]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period
[18]
20.83 200 ns
t
SRY
RDY
X
to clock setup time 2.9 ns
t
RYH
Clock to RDY
X
3.7 ns
t
SGD
GPIF data to clock setup time 3.2 ns
t
DAH
GPIF data hold time 4.5 ns
t
XGD
Clock to GPIF data output propagation delay 15 ns
t
XCTL
Clock to CTL
X
output propagation delay 13.06 ns
IFCLK
SLRD
FLAGS
SLOE
t
SRD
t
RDH
t
OEon
t
XFD
t
XFLG
DATA
t
IFCLK
N+1
t
OEoff
N
Figure 9. Slave FIFO Synchronous Read Timing Diagram
[16]
Table 12. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
[17]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period 20.83 ns
t
SRD
SLRD to clock setup time 18.7 ns
t
RDH
Clock to SLRD hold time 0 ns
t
OEon
SLOE turn-on to FIFO data valid 10.5 ns
t
OEoff
SLOE turn-off to FIFO data hold 2.15 10.5 ns
t
XFLG
Clock to FLAGS output propagation delay 9.5 ns
t
XFD
Clock to FIFO data output propagation delay 11 ns
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