Specifications

CY7C68053
Document # 001-06120 Rev *J Page 27 of 42
9.4 Slave FIFO Asynchronous Read
Table 13. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
[17]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period 20.83 200 ns
t
SRD
SLRD to clock setup time 12.7 ns
t
RDH
Clock to SLRD hold time 3.7 ns
t
OEon
SLOE turn-on to FIFO data valid 10.5 ns
t
OEoff
SLOE turn-off to FIFO data hold 2.15 10.5 ns
t
XFLG
Clock to FLAGS output propagation delay 13.5 ns
t
XFD
Clock to FIFO data output propagation delay 17.31 ns
SLRD
FLAGS
t
RDpwl
t
RDpwh
SLOE
t
XFLG
t
XFD
DATA
t
OEon
t
OEoff
N+1
N
Figure 10. Slave FIFO Asynchronous Read Timing Diagram
[16]
Note
19. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 14. Slave FIFO Asynchronous Read Parameters
[19]
Parameter Description Min Max Unit
t
RDpwl
SLRD pulse width LOW 50 ns
t
RDpwh
SLRD pulse width HIGH 50 ns
t
XFLG
SLRD to FLAGS output propagation delay 70 ns
t
XFD
SLRD to FIFO data output propagation delay 15 ns
t
OEon
SLOE turn-on to FIFO data valid 10.5 ns
t
OEoff
SLOE turn-off to FIFO data hold 2.15 10.5 ns
[+] Feedback