Specifications

CY7C68053
Document # 001-06120 Rev *J Page 29 of 42
9.6 Slave FIFO Asynchronous Write
9.7 Slave FIFO Synchronous Packet End Strobe
DATA
t
SFD
t
FDH
FLAGS
t
XFD
t
WRpwh
t
WRpwl
Figure 12. Slave FIFO Asynchronous Write Timing Diagram
[16]
SLWR
Table 17. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
[19]
Parameter Description Min Max Unit
t
WRpwl
SLWR pulse LOW 50 ns
t
WRpwh
SLWR pulse HIGH 50 ns
t
SFD
SLWR to FIFO data setup time 10 ns
t
FDH
FIFO data to SLWR hold time 10 ns
t
XFD
SLWR to FLAGS output propagation delay 70 ns
FLAGS
t
XFLG
IFCLK
PKTEND
t
SPE
t
PEH
Figure 13. Slave FIFO Synchronous Packet End Strobe Timing Diagram
[16]
Table 18. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
[10]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period 20.83 ns
t
SPE
PKTEND to clock setup time 14.6 ns
t
PEH
Clock to PKTEND hold time 0 ns
t
XFLG
Clock to FLAGS output propagation delay 9.5 ns
Table 19. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
[10]
Parameter Description Min Max Unit
t
IFCLK
IFCLK period 20.83 200 ns
t
SPE
PKTEND to clock setup time 8.6 ns
t
PEH
Clock to PKTEND hold time 3.04 ns
t
XFLG
Clock to FLAGS output propagation delay 13.5 ns
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