Specifications

CY7C68053
Document # 001-06120 Rev *J Page 34 of 42
9.13.2 Single and Burst Synchronous Write
Figure 22 shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the
synchronizing clock. The diagram illustrates a single write
followed by burst write of 3 bytes and committing all 4 bytes as
a short packet using the PKTEND pin.
■ At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied low in some applications)
Note t
SFA
has a minimum of 25 ns. This means that when
IFCLK is running at 48 MHz, the FIFO address setup time is
more than one IFCLK cycle.
■ At t = 1, the external master/peripheral must output the data
value onto the data bus with a minimum setup time of t
SFD
before the rising edge of IFCLK.
■ At t = 2, SLWR is asserted. The SLWR must meet the setup
time of t
SWR
(time from asserting the SLWR signal to the rising
edge of IFCLK) and maintain a minimum hold time of t
WRH
(time
from the IFCLK edge to the deassertion of the SLWR signal).
If the SLCS signal is used, it must be asserted before SLWR
is asserted. (That is, the SLCS and SLWR signals must both
be asserted to start a valid write condition).
■ While the SLWR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented.
The FIFO flag is also updated after a delay of t
XFLG
from the
rising edge of the clock.
The same sequence of events is also shown for a burst write and
is marked with the time indicators of T = 0 through 5.
Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, when the SLWR is asserted, the data on the
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 22, when the four bytes are written to the FIFO,
SLWR is deasserted. The short 4-byte packet can be committed
to the host by asserting the PKTEND signal.
There is no specific timing requirement that needs to be met for
asserting the PKTEND signal with regards to asserting the
SLWR signal. PKTEND can be asserted with the last data value
or thereafter. The only requirement is that the setup time t
SPE
and the hold time t
PEH
must be met. In the scenario of Figure 22,
the number of data values committed includes the last value
written to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND can also be asserted in subsequent clock cycles. The
FIFOADDR lines must be held constant during the PKTEND
assertion.
Although there are no specific timing requirements for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one
byte/word packet. Additional timing requirements exist when the
FIFO is configured to operate in auto mode and you want to send
two packets: a full packet (full defined as the number of bytes in
the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte/word
packet committed manually using the PKTEND pin. In this case,
the external master must make sure to assert the PKTEND pin
at least one clock cycle after the rising edge that caused the last
byte/word to be clocked into the previous auto committed packet
(the packet with the number of bytes equal to what is set in the
AUTOINLEN register). Refer to Figure 14 on page 30 for further
details about this timing.
IFCLK
SLWR
FLAGS
DATA
Figure 22. Slave FIFO Synchronous Write Sequence and Timing Diagram
[16]
t
SWR
t
WRH
t
SFD
t
XFLG
t
IFCLK
N
>= t
SWR
>= t
WRH
N+3
PKTEND
N+2
t
XFLG
t
SFA
t
FAH
t
SPE
t
PEH
FIFOADR
SLCS
t
SFD
t
SFD
t
SFD
N+1
t
FDH
t
FDH
t
FDH
t
FDH
t=0
t=1
t=2
t=3
t
SFA
t
FAH
T=1
T=0
T=2
T=5
T=3
T=4
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