Orange Tree Technologies ZestSC1 User Guide Author Charles Sweeney and Matt Bowen Version 1.
Orange Tree Technologies Version 1.00 1.01 1.02 1.03 1.04 1.05 1.06 Date 02/11/04 01/02/05 17/02/05 07/03/05 28/04/05 14/03/06 04/12/07 Comment First Version Clarifications for power supply and clocks Resettable fuse ratings Added 512 byte transfer restriction Added Verilog support Updated for LP USB interface Added contents of shipping package Rubber feet supplied separately © 2007 Orange Tree Technologies Ltd. All rights reserved.
ZestSC1 User Guide 1 Contents 1 CONTENTS.......................................................................................................................................................... 3 2 GLOSSARY.......................................................................................................................................................... 4 3 REFERENCES..................................................................................................................................
Orange Tree Technologies 2 Glossary DCI Digitally Controlled Impedance DCM Digital Clock Manager Endpoint A USB endpoint is the source or destination of a USB transfer GPIF General Programmable Interface of the USB controller SIE Serial Interface Engine for USB UCF User Constraints File USB Universal Serial Bus 3 References 1. Cypress Semiconductor Corporation, CY7C68013 EZ-USB FX2 USB Microcontroller High-speed USB Peripheral Controller, Rev C, 19th December 2002. 2.
ZestSC1 User Guide 4 Introduction Thank you for purchasing a ZestSC1. This user guide explains how to install the ZestSC1 and how to start using it with some examples. Please read this guide fully before starting to use the ZestSC1. 5 System Requirements 1. A host computer or USB hub with an available USB port. The USB port may be either Full Speed 12Mbps (USB V1.1 or 2.0) or High Speed 480Mbps (USB V2.0). 2. Windows 2000 or Windows XP operating system. 3.
Orange Tree Technologies 6 Installation 6.1 Packing List Please check that the following items are in the package sent to you and contact Orange Tree Technologies if any are missing: 1. 2. 3. 4. 5. 6. 7.
ZestSC1 User Guide standoffs in a position where it cannot touch any other items such as chassis, boards or cables. 7. Plug the USB cable into ZestSC1 and the host computer or USB hub. It does not matter whether the host computer is switched on or off. The cable has different connectors at each end to ensure it is plugged in the correct way round. 8. If the host computer is switched off then switch it on now. 9. The host computer will detect a new USB device and request the software driver. 10.
Orange Tree Technologies Unless otherwise stated, pin 1 is indicated on the PCB by the figure ‘1’. J1 USB B connector J2 Test header for monitoring USB controller signals: Pin 1 2 3 4 J3 USB Controller Signal Port E bit 0 Port E bit 1 Port E bit 2 BreakPoint JTAG header for configuring FPGA: Pin 1 2 3 4 5 6 Page 8 of 57 FPGA JTAG Pin VCC 2.
ZestSC1 User Guide J4 User I/O Header IO pins are connected directly to the FPGA. See UCF for FPGA pin connections. Signal 5V Ground Ground Ground IO0 IO2 IO4 IO6 IO8 IO10 IO12 IO14 IO16 IO18 IO20 IO22 IO24 IO26 IO28 IO30 IO32 IO34 IO36 IO38 IO40 IO42 IO44 CLK_IO_P IO46 Ground Ground Ground J5 Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Signal 3.
Orange Tree Technologies J6 Power source Connect Pins 1-2 2-3 J7 Power Source Power jack J5 or USB Hard disk drive connector J7 PC hard disk power connector Pin 1 2 3 4 Signal No connect Ground Ground 5V 6.3 Software The software driver package includes a Windows Installer utility to perform the installation. To install the software, run the setup.exe utility from the CD and follow the on-screen instructions.
ZestSC1 User Guide 7 Description The block diagram of ZestSC1 is shown in Figure 3. It is a desktop board with a Xilinx Spartan-3 FPGA with up to one million system gates. The FPGA is connected to a host computer over High Speed USB (12 or 480Mbits/sec) for configuration and data communication. A synchronous SRAM of either 1 or 8 MBytes stores application data, and a 32x2 0.1” pitch header can be used for I/O.
Orange Tree Technologies the FIFO interface. The FIFO interface can be controlled by either an internal master in the FX2 or an external master in the FPGA. The internal master is a programmable state machine called the General Programmable Interface or GPIF. Conversely, when the FIFO interface is controlled by the FPGA it is in Slave FIFO mode. There are also general purpose data ports connected between the FX2 and the FPGA.
ZestSC1 User Guide The GPIF also has 6 Ready input signals and 6 Control output signals for general purpose use, and these are all connected to the FPGA. CTL3 and 4 are connected to FPGA configuration CS_n and WRITE_n. These configuration signals are also connected to Port C bits 0 & 1, but for high speed configuration the GPIF Control signals are used. In Slave FIFO mode some of the Ready and Control signals become FIFO control signals.
Orange Tree Technologies 7.1.1.1 FPGA Configuration The GPIF mode is used for configuring the FPGA using the SelectMap port. The FX2 acts as a master driving the FPGA CS_n, WRITE_n and data ports. Data is transferred directly from the USB port to the GPIF master and on to the FPGA using the Auto Out method detailed in [3]. 7.1.1.2 Streaming Data Transfer The slave FIFO mode is used to stream data between the host and FPGA.
ZestSC1 User Guide reversing the data flow, select a large value (256 or greater). For applications which alternate transferring short blocks in either direction, select a short value (such as 16). User_StreamDataIn is the data stream from the host to the FPGA. The active high User_StreamDataInWE signal indicates when the data is valid. If the user application sets User_StreamDataInBusy high then the host will be blocked and no data will be sent to the user application.
Orange Tree Technologies 7.1.1.3 Register Reads and Writes The FX2 external bus is connected to the FPGA allowing memory mapped accesses to registers implemented inside the FPGA. The supplied FPGA files include a reference design to illustrate use of registers.
ZestSC1 User Guide USER CLK USER RegAddr A0 USER RegDataIn D0 A1 USER RegWE D1 USER RegDataOut USER RegRE Figure 6. Register read and write accesses 7.1.1.4 User Signals The 8 user signals between the FPGA and FX2 can be used for any application defined purpose. However, care must be taken to set the direction of the FX2 Port C signals such that the FX2 and FPGA do not drive against each other at any time. Failure to do so may result in damage to the hardware. 7.1.1.
Orange Tree Technologies • I/O – 49 I/O signals, 2 of which can be a differential pair clock input. The I/O signals FPGA banks have 51 ohm impedance reference resistors for Spartan DCI buffers. There are also 8 LEDs D2-9 that share IO signals 0, 1, & 41-46 respectively. These are driven active low. For signal allocations to FPGA pins, see the UCF supplied with the board. The FPGA is configured from the USB in Slave Parallel mode. Alternatively it can be configured using JTAG via header J3.
ZestSC1 User Guide USER_SRAM_A: in std_logic_vector(22 downto 0); USER_SRAM_W: in std_logic; USER_SRAM_R: in std_logic; USER_SRAM_DR_VALID: out std_logic; USER_SRAM_DW: in std_logic_vector(17 downto 0); USER_SRAM_DR: out std_logic_vector(17 downto 0); ------------ 23-bit address write strobe active high read strobe active high read data valid strobe active high 18-bit data bus for writing to SRAM 18-bit data bus for reading from SRAM // // // // // // // // // // // 23-bit address write strobe active h
Orange Tree Technologies the data by 2 further clocks as required by the ZBT SRAM. Byte write strobes are not implemented. For read cycles the user logic drives the read strobe high and the read address in the same clock cycle, and the logic core registers all these signals. Valid data is returned to the user code 4 clocks after the user code drives the read strobe high. The valid data is accompanied by the active high data valid strobe.
ZestSC1 User Guide power switch so is available only after the FX2 has enabled the power switch using its Port E bit 0. The FPGA I/O banks connected to J4 are 3V3. They are NOT 5V tolerant. However 5V signals can be connected to J4 via 180 ohm series resistors to limit the current into each FPGA pin to less than 10mA. As a build option, DCI reference resistors can be fitted for matching the characteristic impedance of the IO lines for DCI buffers.
Orange Tree Technologies J5 D10 D11 D12 D13 J7 D1 J1 D4 D5 D6 D7 D8 D9 D2 D3 J4 Figure 8. Approximate Positions of LEDs 7.6 Clocks The FPGA has two fixed frequency clock inputs of 48MHz each and one clock input from the IO header. The FPGA’s internal DCM’s can be used to synthesise other clock frequencies from 1.5MHz to 280MHz.
ZestSC1 User Guide 2.5W (500mA @ nominal 5V) is available from USB. The following table shows the typical quiescent power consumption of the board when connected to a USB host. The remaining power from the USB 2.5W after allowing for 10% loss in the power supplies is available for operating power and is also shown in the table below. FPGA and Memory Quiescent Power (W) Available Operating Power (W) 400 and 1MB 1.35 1.0 1000 and 1MB 1.40 1.0 1000 and 8MB* 1.80 0.
Orange Tree Technologies 7.8 Build Options The following modifications can be made to the board by arrangement with Orange Tree Technologies. 1. DCI reference resistors for the IO lines. DCI buffers require reference resistors for matching to the characteristic impedance of the IO lines. On ZestSC1 the IO lines are about 50 ohms impedance so the reference resistors are 51 ohms, being the closest standard value.
ZestSC1 User Guide 8 Using the Host Library The ZestSC1 host support software consists of a system driver and a host library to allow access to the board. The system driver is installed automatically during installation of the ZestSC1 support package. The host library consists of a static C library file (.lib file) and an associated C header file (.h file). To use the ZestSC1 support library in your own code, you must include the header file at the start of your program. For example: #include
Orange Tree Technologies 9 Host Utilities A number of utilities are provided with the ZestSC1 support library. These can be found in the Utils sub-directory of the support package installation. 9.1 Bit2C Bit2C.exe converts Xilinx .bit FPGA configuration files to C header files. The C header file contains a static array definition with the raw data from the .bit file. This array can be passed to the ZestSC1RegisterImage function to obtain a handle suitable for the ZestSC1Configure function. In this way, .
ZestSC1 User Guide 10 Examples The ZestSC1 Support package contains a number of examples to illustrate the use of the ZestSC1 and its Host Support Library. The examples are located in the Examples subdirectory of the ZestSC1 installation directory. Each example consists of a host program and a Xilinx XST VHDL or Verilog project. Examples 2 and 4 also contain ModelSim testbenches to illustrate how the various interfaces can be simulated before implementation.
Orange Tree Technologies 11 Host Library Function Reference ZestSC1CountCards ZESTSC1_STATUS ZestSC1CountCards( unsigned long *NumCards, unsigned long *CardIDs, unsigned long *SerialNumbers, ZESTSC1_FPGA_TYPE *FPGATypes); Parameters NumCards CardIDs SerialNumbers FPGATypes Pointer to location to receive total number of ZestSC1 cards in the system. Pointer to buffer to receive list of card IDs in the system. May be NULL. Pointer to buffer to receive list of card serial numbers in the system. May be NULL.
ZestSC1 User Guide unsigned long NumCards; unsigned long *CardIDs; /* Get the number of cards in the system */ ZestSC1CountCards(&NumCards, NULL, NULL, NULL); /* Allocate a buffer to receive the card IDs */ CardIDs = malloc(sizeof(unsigned long) * NumCards); /* Fill in the buffer with the card IDs */ ZestSC1CountCards(&NumCards, CardIDs, NULL, NULL); CONFIDENTIAL Page 29 of 57
Orange Tree Technologies ZestSC1OpenCard ZESTSC1_STATUS ZestSC1OpenCard( unsigned long CardID, ZESTSC1_HANDLE *Handle); Parameters CardId Handle ID of card to open. See ZestSC1CountCards. Pointer to receive the handle of the open card. This handle is used to identify the card in future calls to the ZestSC1 library.
ZestSC1 User Guide ZestSC1GetCardInfo ZESTSC1_STATUS ZestSC1GetCardInfo( ZESTSC1_HANDLE Handle, ZESTSC1_CARD_INFO *Info); Parameters Handle Info Handle of open ZestSC1 card. See ZestSC1OpenCard. Pointer to structure to receive information about the card.
Orange Tree Technologies ZESTSC1_CARD_INFO Info; /* Open a card with ID of 1 */ ZestSC1OpenCard(1, &Handle); /* Obtain information about the card */ ZestSC1GetCardInfo(Handle, &Info); /* Perform action based on FPGAType */ if (Info.FPGAType==ZESTSC1_XC3S400) ZestSC1ConfigureFromFile(Handle, “file400.bit”); else if (Info.FPGAType== ZESTSC1_XC3S1000) ZestSC1ConfigureFromFile(Handle, “file1000.
ZestSC1 User Guide ZestSC1SetTimeOut ZESTSC1_STATUS ZestSC1SetTimeOut( ZESTSC1_HANDLE Handle, unsigned long MilliSeconds); Parameters Handle MilliSeconds Handle of open ZestSC1 card. See ZestSC1OpenCard. Length to required timeout in milliseconds.
Orange Tree Technologies ZestSC1SetCardID ZESTSC1_STATUS ZestSC1SetCardID( ZESTSC1_HANDLE Handle, unsigned long CardID); Parameters Handle CardID Handle of open ZestSC1 card. See ZestSC1OpenCard. Value of new card ID.
ZestSC1 User Guide ZestSC1CloseCard ZESTSC1_STATUS ZestSC1CloseCard(ZESTSC1_HANDLE Handle); Parameters Handle Handle of open ZestSC1OpenCard. ZestSC1 card to close. See Return Value ZESTSC1_SUCCESS ZESTSC1_ILLEGAL_HANDLE ZESTSC1_TIMEOUT Function succeeded Attempt to use illegal card handle Operation timed out Description ZestSC1CloseCard should be called when the specified card is finished with. It frees resources and allows other applications to access the card.
Orange Tree Technologies ZestSC1RegisterErrorHandler ZESTSC1_STATUS ZestSC1RegisterErrorHandler( ZESTSC1_ERROR_FUNC Function); Parameters Function Pointer to error handler function notifications for this application. to receive all error Return Value ZESTSC1_SUCCESS Function succeeded Description ZestSC1RegisterErrorHandler can be called to install a central error handling routine for a user program.
ZestSC1 User Guide /* Other calls to ZestSC1 library here */ /* Note that the return code need not be checked as ErrorHandler will be called for any return values not equal to ZESTSC1_SUCCESS */ } CONFIDENTIAL Page 37 of 57
Orange Tree Technologies ZestSC1GetErrorMessage ZESTSC1_STATUS ZestSC1GetErrorMessage(ZESTSC1_STATUS Status, char **Buffer); Parameters Status Buffer ZestSC1 error code for which description is required. Pointer to location to receive error code description string. Return Value ZESTSC1_SUCCESS ZESTSC1_ILLEGAL_STATUS_CODE Function succeeded Status code is out of range Description ZestSC1GetErrorMessage can be called to obtain a descriptive message for a return status from a ZestSC1 library function.
ZestSC1 User Guide ZestSC1ConfigureFromFile ZESTSC1_STATUS ZestSC1ConfigureFromFile(ZESTSC1_HANDLE Handle, char *FileName); Parameters Handle FileName Handle of open ZestSC1 card. See ZestSC1OpenCard. Name of .bit file to use to configure the FPGA.
Orange Tree Technologies ! Page 40 of 57 Configuring the FPGA with an incorrect BIT file can damage your hardware. Ensure that FPGA pins are connected correctly and do not drive against peripherals on the board.
ZestSC1 User Guide ZestSC1LoadFile ZESTSC1_STATUS ZestSC1LoadFile( char *FileName, ZESTSC1_IMAGE *Image); Parameters FileName Image Name of .bit file to use to configure the FPGA. Pointer to location to receive FPGA configuration image.
Orange Tree Technologies /* Other execution operations here */ /* Configure the FPGA from the image */ ZestSC1Configure(Handle, Image); Page 42 of 57
ZestSC1 User Guide ZestSC1Configure ZESTSC1_STATUS ZestSC1Configure( ZESTSC1_HANDLE Handle, ZESTSC1_IMAGE Image); Parameters Handle Image Handle of open ZestSC1 card. See ZestSC1OpenCard. FPGA configuration image to use to configure the FPGA.
Orange Tree Technologies /* Register the FPGA configuration image */ ZestSC1RegisterImage(Buffer, Length, &Image); /* Other initialization operations here */ /* Open a card with ID of 1 */ ZestSC1OpenCard(1, &Handle); /* Other execution operations here */ /* Configure the FPGA from the image */ ZestSC1Configure(Handle, Image); ! Page 44 of 57 Configuring the FPGA with an incorrect BIT file can damage your hardware.
ZestSC1 User Guide ZestSC1RegisterImage ZESTSC1_STATUS ZestSC1RegisterImage(void *Buffer, unsigned long BufferLength, ZESTSC1_IMAGE *Image); Parameters Buffer BufferLength Image Buffer containing FPGA configuration data. Normally generated by Bit2C utility. Length, in bytes, of the configuration data. Pointer to location to receive FPGA configuration image.
Orange Tree Technologies /* Open a card with ID of 1 */ ZestSC1OpenCard(1, &Handle); /* Other execution operations here */ /* Configure the FPGA from the image */ ZestSC1Configure(Handle, Image); Page 46 of 57
ZestSC1 User Guide ZestSC1FreeImage ZESTSC1_STATUS ZestSC1FreeImage(ZESTSC1_IMAGE Image); Parameters Image FPGA configuration image to free. Return Value ZESTSC1_SUCCESS ZESTSC1_ILLEGAL_IMAGE_HANDLE Function succeeded Attempt to use illegal configuration image handle Description ZestSC1FreeImage should be called when a configuration image handle is no longer needed. It is used to free resources allocated during ZestSC1LoadImage and ZestSC1RegisterImage functions.
Orange Tree Technologies ZestSC1ReadRegister ZESTSC1_STATUS ZestSC1ReadRegister( ZESTSC1_HANDLE Handle, unsigned long Offset, unsigned char *Value); Parameters Handle Offset Value Handle of open ZestSC1 card. See ZestSC1OpenCard. Address of register in FPGA. Pointer to location to receive register value.
ZestSC1 User Guide ZestSC1WriteRegister ZESTSC1_STATUS ZestSC1WriteRegister( ZESTSC1_HANDLE Handle, unsigned long Offset, unsigned char Value); Parameters Handle Offset Value Handle of open ZestSC1 card. See ZestSC1OpenCard. Address of register in FPGA. Value to write to register.
Orange Tree Technologies ZestSC1ReadData ZESTSC1_STATUS ZestSC1ReadData( ZESTSC1_HANDLE Handle, void *Buffer, unsigned long Length); Parameters Handle Buffer Length Handle of open ZestSC1 card. See ZestSC1OpenCard. Buffer to receive the data. Number of bytes to transfer. Must be a multiple of 512.
ZestSC1 User Guide ZestSC1WriteData ZESTSC1_STATUS ZestSC1WriteData( ZESTSC1_HANDLE Handle, void *Buffer, unsigned long Length); Parameters Handle Buffer Length Handle of open ZestSC1 card. See ZestSC1OpenCard. Buffer of data to write. Number of bytes to transfer. Must be a multiple of 512.
Orange Tree Technologies ZestSC1SetSignalDirection ZESTSC1_STATUS ZestSC1SetSignalDirection(ZESTSC1_HANDLE Handle, unsigned char Direction); Parameters Handle Direction Handle of open ZestSC1 card. See ZestSC1OpenCard. Mask of bits for signal direction. A 1 bit indicates a signal from host to FPGA.
ZestSC1 User Guide /* Configure the FPGA */ ZestSC1ConfigureFromFile(Handle, “example.bit”); /* Set the signal to ‘active’ */ ZestSC1SetSignals(Handle, 1); /* Set the signal to ‘inactive’ */ ZestSC1SetSignals(Handle, 0); /* Close the card */ ZestSC1CloseCard(Handle); ! Driving a signal from both the host and FPGA may damage the ZestSC1 hardware.
Orange Tree Technologies ZestSC1SetSignals ZESTSC1_STATUS ZestSC1SetSignals( ZESTSC1_HANDLE Handle, unsigned char Value); Parameters Handle Value Handle of open ZestSC1 card. See ZestSC1OpenCard. Mask of bits to set.
ZestSC1 User Guide /* Set the signal to ‘active’ */ ZestSC1SetSignals(Handle, 1); /* Set the signal to ‘inactive’ */ ZestSC1SetSignals(Handle, 0); /* Close the card */ ZestSC1CloseCard(Handle); ! Driving a signal from both the host and FPGA may damage the ZestSC1 hardware.
Orange Tree Technologies ZestSC1ReadSignals ZESTSC1_STATUS ZestSC1ReadSignals( ZESTSC1_HANDLE Handle, unsigned char *Value); Parameters Handle Value Handle of open ZestSC1 card. See ZestSC1OpenCard. Pointer to location to receive active signals.
ZestSC1 User Guide ZestSC1WaitForInterrupt ZESTSC1_STATUS ZestSC1WaitForInterrupt(ZESTSC1_HANDLE Handle); Parameters Handle Handle of open ZestSC1 card. See ZestSC1OpenCard. Return Value ZESTSC1_SUCCESS ZESTSC1_ILLEGAL_HANDLE ZESTSC1_INTERNAL_ERROR Function succeeded Attempt to use illegal card handle An unspecified internal error occurred while communicating with the driver Operation timed out ZESTSC1_TIMEOUT Description ZestSC1WaitForInterrupt can be used to wait for the FPGA to interrupt the host.
