Datasheet

CY7C1526KV18
CY7C1513KV18
CY7C1515KV18
Document Number: 001-00435 Rev. *R Page 2 of 35
Logic Block Diagram – CY7C1526KV18
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
9
BWS
[0]
V
REF
Write Add. Decode
Write
Reg
18
A
(20:0)
21
9
CQ
CQ
DOFF
Q
[8:0]
9
9
9
Write
Reg
Write
Reg
Write
Reg
C
C
2M x 9 Array 2M x 9 Array 2M x 9 Array 2M x 9 Array
9