Datasheet

CY7C1526KV18
CY7C1513KV18
CY7C1515KV18
Document Number: 001-00435 Rev. *R Page 3 of 35
Logic Block Diagram – CY7C1513KV18
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
36
A
(19:0)
20
18
CQ
CQ
DOFF
Q
[17:0]
18
18
18
Write
Reg
Write
Reg
Write
Reg
C
C
1M x 18 Array 1M x 18 Array 1M x 18 Array 1M x 18 Array
18