Operating instructions

5-3
DFP-R3000
IC
IC
74LCX244SJX (NS)FLAT PACKAGE
SN74HCT244ANS (TI)FLAT PACKAGE
SN74HCT244ANS-E05
G
0
0
x
A
0
1
x
Y
0
1
HI-Z
0
1
x
HI-Z
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
: HIGH IMPEDANCE
1617181920
G2
G1
G1
15
V
DD
GND
14 13 12 11
AY = YA
GG
7654321
2
4
6
8
11
13
15
17
8 9 10
18
16
14
12
9
7
5
3
119
G2
G
OR
2
4
6
8
18
16
14
12
1
11
13
15
17
9
7
5
3
19
G
C-MOS BUS BUFFER WITH 3-STATE OUTPUTS
—TOP VIEW—
AD9696KR-REEL (AD)FLAT PACKAGE
BA10358F-E2 (ROHM)FLAT PACKAGE
UPC358G2-E2
AM29F010-70JC (AMD)
5
6
7
8
9
10
11
12
13
V
DD
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
24
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
CE (E)
OE (G)
WE (W)
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
13
14
15
17
18
19
20
21
PIN
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
—
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
SIGNAL
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
29
28
27
26
25
24
23
22
21
4321323130
14 15 16 17 18 19 20
NC
NC
GND
PIN
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
—
I
SIGNAL
DQ3
DQ4
DQ5
DQ6
DQ7
CE (E)
A10
OE (G)
A11
A9
A8
A13
A14
NC
WE (W)
V
DD
C-MOS 1 M (131,072 x 8)-BIT FLASH EEPROM
—TOP VIEW—
AUTO-SELECT MANUFACTURER CODE (1)
AUTO-SELECT DEVICE CODE (1)
READ
STANDBY
OUTPUT DISABLE
WRITE
ENABLE SECTOR PROTECT
VERIFY SECTOR PROTECT (3)
OPERATION
CE
0
0
0
1
0
0
0
0
INPUT
A0 - A16
CE
OE
WE
OUTPUT
DQ0 - DQ7
; ADDRESS (0 - 16)
; CHIP ENABLE
; OUTPUT ENABLE
; WRITE ENABLE
; DATA (0 - 7)
WE
0
1
X
; LOW LEVEL
; HIGH LEVEL
; DON'T CARE
HI-Z ; HIGH IMPEDANCE
STATE
CONTROL
COMMAND
REGISTER
31
ERASE
VOLTAGE
SWITCH
PROGRAM
VOLTAGE
SWITCH
CE
22
EMBEDDED
ALGORITHMS
OE
24
LOW V
DD
DETECTOR
PROGRAM/
ERASE PULSE
TIMER
A0 - A16
12 - 5
27, 26, 23
25, 4, 28
29, 3, 2
INPUT
OUTPUT
BUFFERS
CHIP ENABLE
OUTPUT ENABLE
LOGIC
Y-DECODER
X-DECODER
ADDRESS LATCH
DATA
LATCH
Y-GATING
1, 048, 576
BIT
CELL
MATRIX
13 - 15
17 - 21
DQ0 - DQ7
OE
0
0
0
X
1
1
VID
0
WE
1
1
1
X
1
0
0
1
A0
0
1
A0
X
X
A0
X
0
A1
0
0
A1
X
X
A1
X
1
A9
VID
VID
A9
X
X
A9
VID
VID
I/O
CODE
CODE
D
OUT
HI-Z
HI-Z
DIN (2)
X
CODE
IN+
IN_
1
2
3
4
8
7
6
5
GND
Q
OUT
Q
OUT
V
CC
V
EE
ULTRAFAST TTL COMPARATOR
—TOP VIEW—
+
_
LATCH
ENABLE
IN
1
2
3
4
8
7
6
5
V
EE
V
CC
_ +
_ +
DUAL OPERATIONAL AMPLIFIERS
(SINGLE-SUPPLY TYPE)
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