Operating instructions
5-6
DFP-R3000
IC
KL5C80A12CFP (KAWASAKI STEEL)
81
85
90
95
100
GND
V
DD
GND
V
DD
50
45
40
35
31
80
75
70
65
60
55
51
V
DD
V
DD
GND
GND
GND
V
DD
GND
1
5
10
15
20
25
30
GND
GND
GND
GND
V
DD
V
DD
V
DD
V
DD
C-MOS HIGH SPEED 8-BIT MPU
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
—
—
I/O
I/O
I/O
O
O
O
O
I/O
I/O
I/O
—
—
—
I/O
I/O
I/O
I/O
—
—
I/O
O
I/O
P33/OUTBP2
V
DD
V
DD
P32/OUTBP1
P31/SYNC
P30/OUTBS0
EMRD
EMWR
EIORD
EIOWR
P27
P26
P25
GND
GND
GND
P24
P23
P22
P21
V
DD
GND
P20
CLK
BFSIO
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I
I
I
I
O
O
O
O
—
O
O
—
O
O
O
O
O
O
—
O
O
O
—
O
O
MODE1
MODE0
ERDY
RXD
TXD
A15
A14
A13
V
DD
A12
A11
GND
A10
A9
A8
A7
A6
A5
V
DD
A4
A3
A2
GND
A1
A0
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I
I/O
—
I/O
I
O
—
—
—
O
O
O
I/O
I/O
I/O
I/O
I/O
D7
V
DD
V
DD
D6
D5
D4
D3
D2
RESET
D1
V
DD
D0
XIN
XOUT
GND
GND
GND
A18/
M1CS
A17/
M0CS
A16
P17/
HALT
P16/
M1
P15/RXC
P14/TXC
P13/XCLK1
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P12/GATEA1
GND
P11/XCLK0
P10/GATEA0
P07/IR7
P06/IR6
P05/IR5
P04/IR4
V
DD
P03/IR3/
NMI
P02/IR2/GATEB2
P01/IR1/GATEB1
P00/IR0/GATEB0
P47/SYNDBD
P46/
RTS
P45/
DTR
P44/
BACK
P43/SYDTIN
P42/
CTS
P41/
DSR
P40/
BREQ
P37/OUTBS2
P36/OUTBP0
P35/OUTA1
P34/OUTA0
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
INPUT
BREQ
CTS
DSR
ERDY
GATEA0
GATEA1
GATEB0
GATEB1
GATEB2
IR0 - IR7
MODE0, MODE1
NMI
RESET
RXC
RXD
SYDTIN
TXC
XCLK0
XCLK1
XIN
OUTPUT
A0 - A18
BACK
CLK
DTR
EIORD
EIOWR
EMRD
EMWR
HALT
M0CS
M1
M1CS
OUTA0
OUTA1
OUTBP0
OUTBP1
OUTBP2
OUTBS0
OUTBS2
RTS
SYNC
SYNDBD
TXD
XOUT
INPUT/OUTPUT
BFSIO
D0 - D7
P00 - P07
P10 - P17
P20 - P27
P30 - P37
P40 - P47
: BUS REQUEST FOR CPU
: CLEAR-TO-SEND SIGNAL FOR USART
: DATA SET READY SIGNAL FOR USART
: WAIT REQUEST FROM THE EXTERNAL DEVICE
: GATE INPUT FOR COUNTER A CHANNEL 0
: GATE INPUT FOR COUNTER A CHANNEL 1
: GATE INPUT FOR COUNTER B CHANNEL 0
: GATE INPUT FOR COUNTER B CHANNEL 1
: GATE INPUT FOR COUNTER B CHANNEL 2
: EXTERNAL INTERRUPT INPUT LEVEL
: MODE SELECT
: NON-MASKABLE INTERRUPT FOR CPU
: RESET
: RECEIVE CLOCK FOR USART
: SERIAL DATA FOR USART
: EXTERNAL SYNC DETECT SIGNAL FOR USART
: TRANSMIT CLOCK FOR USART
: EXTERNAL COUNTER CLOCK FOR COUNTER A CHANNEL0
: EXTERNAL COUNTER CLOCK FOR COUNTER A CHANNEL1
: EXTERNAL CRYSTAL OSCILLATOR
: ADDRESS
: BUS ACKNOWLEDGE FOR CPU
: CLOCK
: DATA TERMINAL READY FOR USART
: EXTERNAL I/O DEVICE READ SIGNAL
: EXTERNAL I/O DEVICE WRITE SIGNAL
: EXTERNAL MEMORY READ SIGNAL
: EXTERNAL MEMORY WRITE SIGNAL
: CPU HALT SIGNAL
: CHIP SELECT FOR EXTERNAL ROM
: M1 CYCLE FOR CPU
: CHIP SELECT FOR EXTERNAL RAM/ROM
: COUNTER A CHANNEL 0
: COUNTER A CHANNEL 1
: PULSE FOR COUNTER B CHANNEL 0
: PULSE FOR COUNTER B CHANNEL 1
: PULSE FOR COUNTER B CHANNEL 2
: STROBE FOR COUNTER B CHANNEL 0
: STROBE FOR COUNTER B CHANNEL 2
: REQUEST-TO-SEND SIGNAL
: SYNC SIGNAL FOR PRE-SCALAR OF COUNTER B
: SYNC DETECT SIGNAL/BREAK DETECT SIGNAL FOR USART
: SERIAL DATA FOR USART
: EXTERNAL CRYSTAL OSCILLATOR
: BUG FINDER PORT
: EXTERNAL DATA BUS
: P0 PORT OF PARALLEL PORT BLOCK A
: P1 PORT OF PARALLEL PORT BLOCK A
: P0 PORT OF PARALLEL PORT BLOCK B
: P1 PORT OF PARALLEL PORT BLOCK B
: P2 PORT OF PARALLEL PORT BLOCK B