Operating instructions
5-9
DFP-R3000
IC
REGULATOR USED FOR POWER SUPPLY
GND GND
CONT
NOISE BYPASS
NOISE BYPASS
V
IN
V
IN
V
OUT
1
6
5
6
4
4
2
3
V
OUT
6
1
V
IN
CONT
3
NOISE BYPASS
CONT
V
OUT
3
1
4
+
_
+
_
THERMAL
PROTECTION
BANDGAP
REFERENCE
—TOP VIEW—
TK11220BMCL
TK11233AUTB (TOKO)
1
2
3
6
5
4
V
OUT
V
IN
NOISE BYPASS
CONT
GND
FIN
6
V
IN
CONT
NOISE BYPASS
4
3
1
V
OUT
NOISE
BYPASS
V
IN
CONT
V
OUT
6
1
THERMAL
PROTECTION
BANDGAP
REFERENCE
+
_
+
_
4
3
REGULATOR USED FOR POWER SUPPLY
—TOP VIEW—
TK16111MTL
V OUT
1
2
3
6
5
4
GND
V IN
V CONT
ANALOG VIDEO SIGNAL DELAYER
—TOP VIEW—
6
4
V IN
V CONT
V OUT
3
V
CC
GND
DEALY
TIME
CONTROLLER
DELAY
LINE
XRD44L60CIV (EXAR)
37
38
39
40
41
42
43
44
45
46
47
48
A-GND
A-V
DD
24
23
22
21
20
19
18
17
16
15
14
13
A-GND
A-V
DD
NC
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
NC
A-GND
A-V
DD
NC
C-MOS CCD IMAGE DIGITIZERS
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
12
—
—
O
O
O
—
—
O
O
O
—
—
NC
NC
DB2
DB3
DB4
D-GND
D-V
DD
DB5
DB6
DB7
NC
NC
13
14
15
16
17
18
19
20
21
22
23
24
O
O
O
I
—
I
—
—
I
I
I
I
DB8
DB9
OVER
OE
A-V
DD
ENABLECAL
A-GND
TEST
STBY1
STBY2
RESET
SCLK
25
26
27
28
29
30
31
32
33
34
35
36
—
I
I
I
I
—
I
I
—
I
I
—
NC
LOAD
SDI
VRT
VRTO
A-V
DD
IN NEG
IN POS
A-GND
VRBO
VRB
NC
37
38
39
40
41
42
43
44
45
46
47
48
I
I
I
I
—
I
—
O
O
O
O
—
CLAMP
SHD
SHP
RSTCCD
A-GND
CLK POL
A-V
DD
SYNC
UNDER
DB0
DB1
NC
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
ADC
PGA
CDS
IN POS
IN NEG
32
31
V
RBO
V
RTO
V
RT
V
RB
GND
V
DD
34
29
28
35
TIMING
GENERATOR
SHD
SHP
RSTCCD
CLAMP
CLK POL
38
39
40
37
42
REG
SERIAL PORT
REGISTERS
SCLK
SDI
LOAD
24
27
26
OFFSET
CALIBRATION
SYNC
OVER
UNDER
44
15
45
OE
ENABLECAL
RESET
STBY2
STBY1
16
18
23
22
21
DB0 - DB9
47, 48,
3 - 5,
8 - 10,
13, 14
XRD44L60CIV (3/3)
INPUT
CLAMP
CLK POL
ENABLECAL
IN NEG
IN POS
LOAD
OE
RESET
RSTCCD
SCLK
SDI
SHD
SHP
STBY1
,
STBY2
VRB
VRBO
VRT
VRTO
OUTPUT
DB0 - DB9
OVR
SYNC
UNDER
: CDS CLAMP CONTROL
: CLOCK POLARITY
: CALIBRATION ENABLE
: CDS INVERTING INPUT
: CDS NON-INVERTING INPUT
: DATA LOAD
: DIGITAL OUTPUT ENABLE
: CHIP RESET
: CCD RESET PULSE DISCONNECT
: SHIFT CLOCK FOR SERIAL REGISTER
: DATA INPUT FOR SERIAL REGISTER
: CDS CLOCK
: CDS CLOCK
: STANDBY CONTROL
: BOTTOM ADC REFERENCE
: INTERNAL BIAS FOR VRB
: TOP ADC REFERENCE
: INTERNAL BIAS FOR VRT
: ANALOG-TO-DIGITAL CONVERTED DATA
: OVER RANGE OUTPUT BIT
: DIGITAL OUTPUT FOR TESTING
: UNDER RANGE OUTPUT BIT