Data Sheet

Document Number: 002-30628 Rev. ** Page 22 of 46
PRELIMINARY
CYBT-213066-02
CYBT-213067-02
PWM
The CYBT-213066-02/CYBT-213067-02 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following:
■ Each of the six PWM channels contains the following registers:
❐ 16-bit initial value register (read/write)
❐ 16-bit toggle register (read/write)
❐ 16-bit PWM counter value register (read)
■ PWM configuration register shared among PWM0–5 (read/write). This 18-bit register is used:
❐ To configure each PWM channel
❐ To select the clock of each PWM channel
❐ To change the phase of each PWM channel
The application can access the PWM module through the FW driver.
Figure 12 shows the structure of one PWM channel.
Figure 12. PWM Block Diagram
PDM Microphone
The CYBT-213066-02/CYBT-213067-02 accepts a ΣΔ-based one-bit pulse density modulation (PDM) input stream and outputs
filtered samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog
microphone signals and generate digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can
be supported:
■ 8 kHz
■ 16 kHz
The external digital microphone takes in a 2.4-MHz clock generated by the CYBT-213066-02/CYBT-213067-02 and outputs a PDM
signal, which is registered by the PDM interface with either the rising or falling edge of the 2.4-MHz clock selectable through a
programmable control bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible.