Specifications

Document Number: 002-30672 Rev. ** Page 19 of 46
PRELIMINARY
CYBT-243068-02
CYBT-243069-02
True Random Number Generator
The CYBT-243068-02/CYBT-243069-02 includes a hardware TRNG (True Random Number Generator). Applications can access the
random number generator via firmware APIs.
Peripherals and Communication Interfaces
I
2
C
The CYBT-243068-02/CYBT-243069-02 provides a 2-pin I
2
C master/slave interface to communicate with I
2
C compatible peripherals.
The following transfer clock rates are supported:
■ 100 kHz
■ 400 kHz
■ 800 kHz (Not a standard I
2
C-compatible speed)
■ 1 MHz (Compatibility with high-speed I
2
C-compatible devices is not guaranteed)
The I
2
C compatible master is capable for doing read, write, write followed by read, and read followed by write operations where
read/write can be up to 64 bytes.
SCL and SDA lines can be routed to any of the configurable GPIOs (as indicated in Table 5), allowing for flexible system configuration.
When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. I
2
C does not support
multimaster capability or flexible wait-state insertion by either master or slave devices.
HCI UART Interface
CYBT-243068-02/CYBT-243069-02 includes a UART interface for factory programming as well as when operating as a BT HCI device
in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable
baud rates from 115200 bps to 3 Mbps. Typical rates are 115200, 921600, 1500000, and 3,000,000 bps although intermediate speeds
are also available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific
command. The CYBT-243068-02/CYBT-243069-02 UART operates correctly with the host UART as long as the combined baud rate
error of the two devices is within ±5%. The UART interface CYBT-243068-02/CYBT-243069-02 has a 1040-byte receive FIFO and a
1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The
default baud rate for H4 is 115.2 kbaud.
During HCI Mode, the DEV_WAKE signal can be programmed to wake up the CYBT-243068-02/CYBT-243069-02 or allow the
CYBT-243068-02/CYBT-243069-02 to sleep when radio activities permit. The CYBT-243068-02/CYBT-243069-02 can also wake up
the host as needed or allow the host to sleep via the HOST_WAKE signal. Combined, the two signals allow the host and the
CYBT-243068-02/CYBT-243069-02 to optimize system power consumption by allowing independent control of low power modes.
DEV_WAKE and HOST_WAKE signals can be enabled via a vendor-specific command.
The FW UART driver allows applications to select different baud rates.
Peripheral UART Interface
The CYBT-243068-02/CYBT-243069-02 has a second UART that may be used to interface to peripherals. Functionally, the peripheral
UART is the same as the HCI UART except for 256-byte TX/RX FIFOs. The peripheral UART is accessed through the I/O ports, which
can be configured individually and separately for each functional pin. The CYBT-243068-02/CYBT-243069-02 can map the peripheral
UART to any GPIO.
Serial Peripheral Interface
The CYBT-243068-02/CYBT-243069-02 has two independent SPI interfaces. Both interfaces support single, dual, and Quad Mode
SPI operations. Either interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer.
To support more flexibility for user applications, the CYBT-243068-02/CYBT-243069-02 has optional I/O ports that can be configured
individually and separately for each functional pin.
SPI IO voltage depends on VDDO.
Keyboard Scanner
The CYBT-243068-02/CYBT-243069-02 includes a HW key scanner that supports a maximum matrix size of 20 × 8. The scanner has
eight inputs (also referred to as rows) and 20 outputs (also referred to as columns). Keys are detected by driving the columns down
sequentially and sampling the rows. The HW scanner includes support for ghost key detection and debouncing. The scanner can also
operate in Sleep and PDS modes allowing low power operation while continuing to detect/store all key strokes, up or down. In other
low power modes, the scanner can continue to monitor the matrix and initiate exit to Active Mode upon detecting a change of state.
The application can access the key scanner via the associated firmware driver. Refer to the Firmware section for more details.