Specifications

Document Number: 002-30672 Rev. ** Page 33 of 46
PRELIMINARY
CYBT-243068-02
CYBT-243069-02
SPI Timing
The SPI interface can be clocked up to 24 MHz.
Table 26 and Figure 14 show the timing requirements when operating in SPI Mode 0 and 2.
Figure 14. SPI Timing, Mode 0 and 2
Table 27 and Figure 15 show the timing requirements when operating in SPI Mode 1 and 3.
Table 26. SPI Mode 0 and 2
Reference Characteristics Min Max Unit
1 Time from master assert SPI_CSN to first clock edge 45 – ns
2 Setup time for MOSI data lines 6 ¾
SCK ns
3 Idle time between subsequent SPI transactions 1 SCK – ns
Table 27. SPI Mode 1 and 3
Reference Characteristics Min Max Unit
1 Time from master assert SPI_CSN to first clock edge 45 – ns
2 Setup time for MOSI data lines 6 ¾
SCK ns
3 Idle time between subsequent SPI transactions 1 SCK – ns