Specifications

Document Number: 002-30672 Rev. ** Page 34 of 46
PRELIMINARY
CYBT-243068-02
CYBT-243069-02
Figure 15. SPI Timing, Mode 1 and 3
I
2
C Compatible Interface Timing
The specifications in Table 27 references Figure 16.
Table 28. I2C Interface Timing Specifications (up to 1 MHz)
Reference Characteristics Min Max Unit
1 Clock frequency –
100 kHz
400 kHz
800 kHz
1000 kHz
2 START condition setup time 650 – ns
3 START condition hold time 280 – ns
4 Clock low time 650 – ns
5 Clock high time 280 – ns
6 Data input hold time
[15]
0 – ns
7 Data input setup time 100 – ns
8 STOP condition setup time 280 – ns
9 Output valid from clock – 400 ns
10 Bus free time
[16]
650 – ns
Notes
15. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
16. Time that the CBUS must be free before a new transaction can start.