Asynchronous Interface Specification Sheet

ManualsBrandsCypress ManualsNetwork CardAN6077

February 19, 2008 Document No. 001-15342 Rev. ** 1

with FX2LP

Implementing an 8-Bit Asynchronous Interface

Application Note Abstract

This application note discusses how to configure the General Programmable Interface (GPIF) and slave FIFOs of the EZ-USB

FX2LP™ to implement an 8-bit asynchronous interface. The GPIF is a programmable 8 or 16-bit parallel interface that reduces

system costs by providing a glueless interface between the EZ-USB FX2LP and different types of external peripherals. The

GPIF allows the EZ-USB FX2LP to perform local bus mastering to external peripherals implementing a wide variety of protocols.

For example, EIDE/ATAPI, printer parallel port (IEEE P1284), Utopia, and other interfaces are supported using the GPIF block

of the EZ-USB FX2LP. In this example, it masters the slave FIFO interface of another EZ-USB FX2LP.

This implementation uses the GPIF Designer (an utility Cypress provides to create GPIF waveform descriptors) to design the

application specific physical layer. The firmware is based on the Cypress EZ-USB FX2LP firmware ‘frameworks’. A hardware

setup of two back-to-back EZ-USB FX2LP boards is also used, one acting as a master and another as a slave. Familiarity with

the EZ-USB FX2LP development kit, examples and documentation on the development kit CD-ROM, and chapters 9 (EZ-USB

FX2LP Slave FIFOs) and 10 (GPIF) of the EZ-USB FX2LP Technical Reference Manual is assumed

Introduction

The objective of this application note is to:

■ Demonstrate a glueless interface to an 8-bit peripheral

data bus (the FIFO of a slave EZ-USB FX2LP).

■ Use EZ-USB FX2LP to transfer data to and from the pe-

ripheral (slave EZ-USB FX2LP) and the USB host.

This application note discusses the necessary hardware con-

nections, internal register settings, and 8051 firmware imple-

mented to execute data transactions over the interface and

across the USB bus.

Figure 1. Hardware Connection Diagram

AN6077

Author: Sonia Gandhi

Associated Project: No

Associated Part Family: CY7C68013A

GET FREE SAMPLES HERE

Software Version: None

Associated Application Notes: None

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Summary of content (23 pages)

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Implementing an 8-Bit Asynchronous Interface with FX2LP AN6077 Author: Sonia Gandhi Associated Project: No Associated Part Family: CY7C68013A GET FREE SAMPLES HERE Software Version: None Associated Application Notes: None Application Note Abstract This application note discusses how to configure the General Programmable Interface (GPIF) and slave FIFOs of the EZ-USB FX2LP™ to implement an 8-bit asynchronous interface.
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AN6077 GPIF Master Pin Descriptions FD[0:7] The GPIF pin names, descriptions, and their uses are discussed in this section. This is Port B, which is configured as the 8-bit data bus. If the WORDWIDE bit of the IFCONFIG register is set, then port D is configured to be FD[8:15]. This implementation has an 8-bit interface. RDYn Inputs RDY[5:0] are ‘ready’ inputs that can be sampled and allow a transaction to wait (inserting wait states), continue, or repeat until the signal is at the appropriate level.
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AN6077 Figure 2 shows the GPIF Designer view of the FIFO Read waveform. This results in the following sequence: s0 When creating the FIFOWR waveform the following timing parameters must be met. Sample the full flag of the peripheral. If the peripheral is ‘not full’, proceed to s1, otherwise proceed to s6 to trigger an interrupt and abort the GPIF waveform.
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AN6077 Figure 4. FIFO Read Waveform in gpif.c Figure 5. FIFO Write Waveform in gpif.c 8051 Firmware Programming (Master) OUTs (FIFO Writes) This section describes how to configure the 8051 to support the interface on the master side (register settings and others) and discusses the firmware implemented to perform data transactions over the local bus and the USB. The complete code listing is provided at the end of this document.
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AN6077 The firmware uses the AUTO mode for both IN and OUT transfers. This means that the maximum size (512 bytes) packets are committed automatically from the peripheral domain to the USB domain for OUT transfers. For IN transfers, they are committed from USB to the peripheral domain. The 8051 is not involved in committing packets. Short packets are handled by the master strobing the PKTEND of the slave. In this implementation, the PKTEND of the slave is tied to CTL2 of the master.
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AN6077 IOA = 0x80; xFIFOTC_OUT = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL ); // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write transaction(s) SYNCDELAY; GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // once master (GPIF) drains OUT packet, it (re)arms to usb domain // this path is always auto, meaning core handles it if( xFIFOTC_OUT < enum_pkt_size ) { // handle short packet to peripheral // wait for the transaction to terminate naturally while( !(
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AN6077 // // // // // if( EP68FIFOFLGS & 0x01 ) { EP6FF=1, when fifo "full" } else { EP6FF=0, when fifo "not full", for example, buffer available setup GPIF transaction count SYNCDELAY; EP6GPIFTCH = 0x02; SYNCDELAY; EP6GPIFTCL = 0x00; trigger FIFO read transaction(s), using SFR SYNCDELAY; GPIFTRIG = GPIFTRIGRD | GPIF_EP6; wait for transaction to terminate naturally SYNCDELAY; while( !( GPIFTRIG & 0x80 ) ) { ; // poll GPIFTRIG.
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AN6077 Code Listing for Master Side #pragma NOIV #include "fx2.h" #include "fx2regs.h" #include "fx2sdly.h" // Do not generate interrupt vectors extern extern extern extern // Received setup data flag BOOL BOOL BOOL BOOL GotSUD; Sleep; Rwuen; Selfpwr; BYTE Configuration; BYTE AlternateSetting; // SYNCDELAY macro // Current configuration // Alternate settings // proto's from "gpif.
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AN6077 // EP4 and EP8 are not used in this implementation SYNCDELAY; // EP4CFG = 0x20; // clear valid bit SYNCDELAY; // EP8CFG = 0x60; // clear valid bit SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = 0x80; 0x82; 0x84; 0x86; 0x88; 0x00; // // // // // // // // // // // // activate NAK-ALL to avoid race conditions reset, FIFO 2 reset, FIFO 4 reset, FIFO 6 reset, FIFO 8 deactivate NAK-ALL // 8-bit bus (WORDWIDE=0)
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AN6077 } #define GPIFTRIGWR 0 #define GPIFTRIGRD 4 #define #define #define #define GPIF_EP2 GPIF_EP4 GPIF_EP6 GPIF_EP8 0 1 2 3 void TD_Poll( void ) { // Called repeatedly while the device is idle static WORD xFIFOTC_OUT = 0x0000; static WORD xFIFOTC_IN = 0x0000; // // // // // // // // // // // // // Registers which require a synchronization delay, see section 15.
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AN6077 // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write transaction(s), using SFR SYNCDELAY; GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // once master (GPIF) drains OUT packet, it (re)arms to usb domain // this path is always auto, meaning core handles it if( xFIFOTC_OUT < enum_pkt_size ) { // handle short packet to peripheral // wait for the transaction to terminate naturally while( !( GPIFTRIG & 0x80 ) ) { ; // poll GPIFTRIG.7, DONE bit.
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AN6077 // RDY0=1, when peripheral is "not empty" // drive FIFOADDR lines OEA = 0xC0; IOA = 0x00; if( EP68FIFOFLGS & 0x01 ) { // EP6FF=1, when fifo "full" } else { // EP6FF=0, when fifo "not full", for example, buffer available // setup GPIF transaction count SYNCDELAY; EP6GPIFTCH = 0x02; SYNCDELAY; EP6GPIFTCL = 0x00; // trigger FIFO read transaction(s), using SFR SYNCDELAY; GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // wait for the transaction to terminate naturally SYNCDELAY; while( !( GPIFTRIG & 0x80 ) ) { ; // p
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AN6077 } BOOL TD_Suspend( void ) { // Called before the device goes into suspend mode return( TRUE ); } BOOL TD_Resume( void ) { // Called after the device resumes return( TRUE ); } //----------------------------------------------------------------------------// Device Request hooks // The following hooks are called by the end point 0 device request parser.
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AN6077 { // Called when a Set Interface command is received EP0BUF[ 0 ] = AlternateSetting; EP0BCH = 0; EP0BCL = 1; return( TRUE ); // Handled by user code } BOOL DR_GetStatus( void ) { return( TRUE ); } BOOL DR_ClearFeature( void ) { return( TRUE ); } BOOL DR_SetFeature( void ) { return( TRUE ); } //----------------------------------------------------------------------------// USB Interrupt Handlers // The following functions are called by the USB interrupt jump table.
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AN6077 EZUSB_IRQ_CLEAR( ); USBIRQ = bmURES; // Clear URES IRQ } void ISR_Susp( void ) interrupt 0 { Sleep = TRUE; EZUSB_IRQ_CLEAR( ); USBIRQ = bmSUSP; } void ISR_Highspeed( void ) interrupt 0 { if ( EZUSB_HIGHSPEED( ) ) { pConfigDscr = pHighSpeedConfigDscr; pOtherConfigDscr = pFullSpeedConfigDscr; } else { pConfigDscr = pFullSpeedConfigDscr; pOtherConfigDscr = pHighSpeedConfigDscr; } EZUSB_IRQ_CLEAR( ); USBIRQ = bmHSGRANT; } void { } void { } void { } void { } void { } void { } void { } void { } void { }
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AN6077 } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { ISR_Ep1pingnak( void ) interrupt 0 ISR_Ep2pingnak( void ) interrupt 0 ISR_Ep4pingnak( void ) interrupt 0 ISR_Ep6pingnak( void ) interrupt 0 ISR_Ep8pingnak( void ) interrupt 0 ISR_Errorlimit( void ) interrupt 0 ISR_Ep2piderror( void ) interrupt 0 ISR_Ep4piderror( void ) interrupt 0 ISR_Ep6piderror( void )
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AN6077 } void ISR_Ep8fflag( void ) interrupt 0 { } void ISR_GpifComplete( void ) interrupt 0 { } void ISR_GpifWaveform( void ) interrupt 0 { // FIFORd WF detected peripheral prematurely empty (less than max. pkt. size) GPIFABORT = 0xFF; INPKTEND = 0x06; SYNCDELAY; EXIF &= ~0x40; INT4CLR = 0xFF; SYNCDELAY; // abort to handle shortpkt // automatically enabled at POR } Code Listing for the Slave Side #pragma NOIV #include "fx2.h" #include "fx2regs.h" #include "fx2sdly.
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AN6077 // // // // // PINFLAGSxx EPxFIFOIE GPIFIE UDMACRCH:L GPIFTRIG SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = SYNCDELAY; FIFORESET = EPxFIFOIRQ GPIFIRQ GPIFADRH:L EPxGPIFTRIG 0x80; 0x82; 0x84; 0x86; 0x88; 0x00; SYNCDELAY; PINFLAGSAB = 0xEF; SYNCDELAY; PINFLAGSCD = 0x98; SYNCDELAY; PORTACFG |= 0x80; SYNCDELAY; FIFOPINPOLAR = 0x00; SYNCDELAY; // // // // // // // // // // // activate NAK-ALL to avoid race conditions see TRM sec
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AN6077 EP2FIFOCFG = 0x10; SYNCDELAY; // AUTOOUT=1, WORDWIDE=0 EP6FIFOCFG = 0x0C; SYNCDELAY; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0 } void TD_Poll( void ) { // Called repeatedly while the device is idle // nothing to do;slave fifo's are in AUTO mode } BOOL TD_Suspend( void ) { // Called before the device goes into suspend mode return( TRUE ); } BOOL TD_Resume( void ) { // Called after the device resumes return( TRUE ); } //----------------------------------------------------------------------------// Devi
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AN6077 EP0BUF[ 0 ] = Configuration; EP0BCH = 0; EP0BCL = 1; return(TRUE); // Handled by user code } BOOL DR_SetInterface( void ) { // Called when a Set Interface command is received AlternateSetting = SETUPDAT[ 2 ]; return( TRUE ); // Handled by user code } BOOL DR_GetInterface( void ) { // Called when a Set Interface command is received EP0BUF[ 0 ] = AlternateSetting; EP0BCH = 0; EP0BCL = 1; return( TRUE ); // Handled by user code } BOOL DR_GetStatus( void ) { return( TRUE ); } BOOL DR_ClearFeature( void
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AN6077 USBIRQ = bmSOF; // Clear SOF IRQ } void ISR_Ures( void ) interrupt 0 { if ( EZUSB_HIGHSPEED( ) ) { pConfigDscr = pHighSpeedConfigDscr; pOtherConfigDscr = pFullSpeedConfigDscr; } else { pConfigDscr = pFullSpeedConfigDscr; pOtherConfigDscr = pHighSpeedConfigDscr; } EZUSB_IRQ_CLEAR( ); USBIRQ = bmURES; // Clear URES IRQ } void ISR_Susp( void ) interrupt 0 { Sleep = TRUE; EZUSB_IRQ_CLEAR( ); USBIRQ = bmSUSP; } void ISR_Highspeed( void ) interrupt 0 { if ( EZUSB_HIGHSPEED( ) ) { pConfigDscr = pHighSp
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AN6077 } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { } void { ISR_Ep4inout( void ) interrupt 0 ISR_Ep6inout( void ) interrupt 0 ISR_Ep8inout( void ) interrupt 0 ISR_Ibn( void ) interrupt 0 ISR_Ep0pingnak( void ) interrupt 0 ISR_Ep1pingnak( void ) interrupt 0 ISR_Ep2pingnak( void ) interrupt 0 ISR_Ep4pingnak( void ) interrupt 0 ISR_Ep6pingnak( void ) interrupt 0 ISR
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AN6077 } void { } void { } void { } void { } void { } void { } void { } void { } ISR_Ep6eflag( void ) interrupt 0 ISR_Ep8eflag( void ) interrupt 0 ISR_Ep2fflag( void ) interrupt 0 ISR_Ep4fflag( void ) interrupt 0 ISR_Ep6fflag( void ) interrupt 0 ISR_Ep8fflag( void ) interrupt 0 ISR_GpifComplete( void ) interrupt 0 ISR_GpifWaveform( void ) interrupt 0 EZ-USB FX2LP is a trademark of Cypress Semiconductor Corp.