nvSRAM Specification Sheet

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STK14CA8

128Kx8 AutoStore™ nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document Number: 001-51592 Rev. ** Revised March 04, 2009

Features

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25, 35, 45 ns Read Access and Read/Write Cycle Time

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Unlimited Read/Write Endurance

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Automatic Nonvolatile STORE on Power Loss

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Nonvolatile STORE Under Hardware or Software Control

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Automatic RECALL to SRAM on Power Up

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Unlimited RECALL Cycles

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200K STORE Cycles

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20-Year Nonvolatile Data Retention

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Single 3.0V + 20%, -10% Operation

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Commercial and Industrial Temperatures

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Small Footprint SOIC and SSOP Packages (RoHS Compliant)

Description

The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-

atile QuantumTrap™ storage element included with each

memory cell. This SRAM provides fast access and cycle times,

ease of use, and unlimited read and write endurance of a normal

SRAM.

Data transfers automatically to the nonvolatile storage cells

when power loss is detected (the STORE operation). On power

up, data is automatically restored to the SRAM (the RECALL

operation). Both STORE and RECALL operations are also

available under software control.

The Cypress nvSRAM is the first monolithic nonvolatile memory

to offer unlimited writes and reads. It is the highest performing

and most reliable nonvolatile memory available.

ROW DECODER INPUT BUFFERS

COLUMN DEC

COLUMN I/O

POWER

CONTROL

HSB

STORE/

RECALL

CONTROL

SOFTWARE

DETECT

– A

Quantum Trap

1024 X 1024

STATIC RAM

ARRAY

1024 X 1024

STORE

RECALL

CAP

Logic Block Diagram

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Summary of content (16 pages)

PAGE 1
STK14CA8 128Kx8 AutoStore™ nvSRAM Features Description ■ 25, 35, 45 ns Read Access and Read/Write Cycle Time ■ Unlimited Read/Write Endurance ■ Automatic Nonvolatile STORE on Power Loss ■ Nonvolatile STORE Under Hardware or Software Control The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvolatile QuantumTrap™ storage element included with each memory cell. This SRAM provides fast access and cycle times, ease of use, and unlimited read and write endurance of a normal SRAM.
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STK14CA8 Pinouts Figure 1. 48-Pin SSOP Figure 2.
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STK14CA8 Absolute Maximum Ratings NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS Voltage on Input Relative to Ground.................–0.5V to 4.1V Voltage on Input Relative to VSS ...........–0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB ......................–0.5V to (VCC + 0.5V) Temperature under Bias ............................... –55°C to 125°C Junction Temperature ................................... –55°C to 140°C Storage Temperature ....................................
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STK14CA8 AC Test Conditions Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times ................................................. ≤ 5 ns Input and Output Timing Reference Levels .................... 1.5V Output Load..................................See Figure 4 and Figure 5 Capacitance (TA = 25°C, f = 1.
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STK14CA8 SRAM READ Cycles #1 and #2 Symbols NO. #1 3 #2 Alt.
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STK14CA8 SRAM WRITE Cycles #1 and #2 NO. Symbols #1 #2 STK14CA8-25 STK14CA8-35 STK14CA8-45 Parameter Alt.
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STK14CA8 AutoStore/POWER UP RECALL NO. Symbols STK14CA8 Parameter Standard Alternate Min Power up RECALL Duration Units Notes 20 ms 9 10, 11 Max 22 tHRECALL 23 tSTORE STORE Cycle Duration 12.5 ms 24 VSWITCH Low Voltage Trigger Level 2.65 V 25 VCCRISE VCC Rise Time tHLHZ 150 μs t Figure 10. AutoStore/POWER UP RECALL 25 23 22 23 22 Note Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. Notes 9.
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STK14CA8 Software Controlled STORE/RECALL Cycle NO. Symbols E Cont G Cont Parameter[12,13] Alt STK14CA8-35 STK14CA8-35 STK14CA8-45 Min Max Min Max Min Max Units Notes 26 tAVAV tAVAV tRC STORE/RECALL Initiation Cycle Time 25 35 45 ns 27 tAVEL tAVGL tAS Address Setup Time 0 0 0 ns 28 tELEH tGLGH tCW Clock Pulse Width 20 25 30 ns 29 tEHAX tGHAX Address Hold Time 1 1 1 ns 30 tRECALL tRECALL RECALL Duration 50 50 50 13 μs Figure 11.
PAGE 9
STK14CA8 Hardware STORE Cycle NO. Symbols Standard 31 tDELAY 32 tHLHX Parameter Alternate tHLQZ STK14CA8 Min Max Hardware STORE to SRAM Disabled 1 70 Hardware STORE Pulse Width 15 Units Notes μs 14 ns Figure 13. Hardware STORE Cycle 32 23 31 Soft Sequence Commands Symbols NO. 33 Parameter Standard tSS STK14CA8 Min Soft Sequence Processing Time Units Notes μs 15, 16 Max 70 Figure 14. Software Sequence Commands 33 33 Notes 14.
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STK14CA8 Mode Selection E W G A16-A0 Mode I/O Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output Data Output Data Output Data Output Data Output Data Output Data Active 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoSto
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STK14CA8 SRAM READ The STK14CA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-16 determine which of the 131,072 data bytes are accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs are valid at tELQV or at tGLQV, whichever is later (READ cycle #2).
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STK14CA8 Software STORE Data Protection Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements.
PAGE 13
STK14CA8 Low Average Active Power CMOS technology provides the STK14CA8 with the benefit of power supply current that scales with cycle time. Less current is drawn as the memory cycle time becomes longer than 50 ns. Figure 16 shows the relationship between ICC and READ/WRITE cycle time. Worst case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled.
PAGE 14
STK14CA8 Ordering Information STK14CA8-R F 45 ITR Packing Option Blank=Tube TR=Tape and Reel Temperature Range Blank=Commercial (0 to +70 C) I= Industrial (-45 to +85 C) Access Time 25=25 ns 35=35 ns 45=45 ns Lead Finish F=100% Sn (Matte Tin) RoHS Compliant Package N=Plastic 32-pin 300 mil SOIC (50 mil pitch) R=Plastic 48-pin 300 mil SSOP (25 mil pitch) Ordering Codes Part Number Description Access Times Temperature STK14CA8-NF25 3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Commercial STK14CA8-NF35
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STK14CA8 Package Diagrams Figure 17. 32-Pin 300 mil SOIC (51-85127) 51-85127 *A Figure 18. 48-Pin 300 mil SSOP (51-85061) 51-85061 *C Document Number: 001-51592 Rev.
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STK14CA8 Document History Page Document Title: STK14CA8 128Kx8 AutoStore™ nvSRAM Document Number: 001-51592 Revision ECN Orig. of Change Submission Date ** 2665610 GVCH/PYRS 02/04/09 Description of Change New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.