nvSRAM Specification Sheet

STK14CA8
Document Number: 001-51592 Rev. ** Page 10 of 16
Mode Selection
E W G A
16
-A
0
Mode I/O Power Notes
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x08B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
17, 18, 19
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
17, 18, 19
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active 17, 18, 19
0x08FC0 Nonvolatile Store Output High Z I
CC2
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
17, 18, 19
Notes
17. The six consecutive addresses must be in the order listed. W
must be high during all six consecutive cycles to enable a nonvolatile cycle.
18. While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes
19. I/O state depends on the state of G
. The I/O table shown assumes G low
[+] Feedback