Evaluation Pod Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCapSense CY8C20x36

CapSense™ Applications

CY8C20x36/46/66, CY8C20396

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-12696 Rev. *D Revised March 17, 2009

Features

■ 1.71V to 5.5V Operating Range

■ Low Power CapSense™ Block

❐ Configurable Capacitive Sensing Elements

❐ Supports Combination of CapSense Buttons, Sliders,

Touchpads, Touch Screens, and Proximity Sensor

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds Running to 24 MHz

❐ Low Power at High Speed

❐ Interrupt Controller

❐ Temperature Range: -40°C to +85°C

■ Flexible On-Chip Memory

❐ Three Program/Data Storage Size Options:

• CY8C20x36: 8K Flash / 1K SRAM

• CY8C20x46: 16K Flash / 2K SRAM

• CY8C20x66: 32K Flash / 2K SRAM

❐ 50,000 Flash Erase/Write Cycles

❐ Partial Flash Updates

❐ Flexible Protection Modes

❐ In-System Serial Programming (ISSP)

■ Full-Speed USB

❐ Available on CY8C20396 and CY8C20666 Only

❐ 12 Mbps USB 2.0 Compliant

❐ Eight Unidirectional Endpoints

❐ One Bidirectional Control Endpoint

❐ Dedicated 512 Byte Buffer

❐ Internally Regulated at 3.3V

■ Precision, Programmable Clocking

❐ Internal Main Oscillator: 6/12/24 MHz ± 5%

❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and

Sleep Timers

❐ Precision 32 kHz Oscillator for Optional External Crystal

(CY8C20x46/66 only)

❐ 0.25% Accuracy for USB with No External Components

(CY8C20396 and CY8C20666 only)

■ Programmable Pin Configurations

❐ Up to 36 GPIO (Depending on Package)

❐ Dual Mode GPIO: All GPIO Support Digital IO and Analog

Input

❐ 25 mA Sink Current on All GPIO

❐ Pull up, High Z, Open Drain Modes on All GPIO

❐ CMOS Drive Mode(5 mA Source Current) on Ports 0 and 1:

• 20 mA (at 3.0V) Total Source Current on Port 0

• 20 mA (at 3.0V) Total Source Current on Port 1

❐ Selectable, Regulated Digital IO on Port 1

❐ Configurable Input Threshold on Port 1

❐ Hot Swap Capability on all Port 1 GPIO

■ Versatile Analog Mux

❐ Common Internal Analog Bus

❐ Simultaneous Connection of IO

❐ High PSRR Comparator

❐ Low Dropout Voltage Regulator for All Analog Resources

■ Additional System Resources

❐ I

C™ Slave:

• Selectable to 50 kHz, 100 kHz, or 400 kHz

• No Clock Stretching Required (under most conditions)

• Implementation During Sleep Modes with Less Than

100 µA

• Hardware Address Validation

❐ SPI™ Master and Slave: Configurable 46.9 kHz - 12 MHz

❐ Three 16-Bit Timers

❐ Watchdog and Sleep Timers

❐ Internal Voltage Reference

❐ Integrated Supervisory Circuit

■ Complete Development Tools

❐ Free Development Tool (PSoC Designer™)

❐ Full Featured, In-Circuit Emulator and Programmer

❐ Full Speed Emulation

❐ Complex Breakpoint Structure

❐ 128K Trace Memory

■ Package Options

❐ CY8C20x36:

• 16-Pin 3 x 3 x 0.6 mm QFN

• 24-Pin 4 x 4 x 0.6 mm QFN

• 32-Pin 5 x 5 x 0.6 mm QFN

❐ CY8C20x46:

• 16-Pin 3 x 3 x 0.6 mm QFN

• 24-Pin 4 x 4 x 0.6 mm QFN

• 32-Pin 5 x 5 x 0.6 mm QFN

❐ CY8C20396: 24-Pin 4 x 4 x 0.6 mm QFN

❐ CY8C20x66:

• 32-Pin 5 x 5 x 0.6 mm QFN

• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)

• 48-Pin SSOP

[+] Feedback

Summary of content (34 pages)

PAGE 1
CY8C20x36/46/66, CY8C20396 CapSense™ Applications Features ■ 1.71V to 5.
PAGE 2
CY8C20x36/46/66, CY8C20396 Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 1.8/2.
PAGE 3
CY8C20x36/46/66, CY8C20396 PSoC® Functional Overview Figure 1. Analog System Block Diagram The PSoC family consists of on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect.
PAGE 4
CY8C20x36/46/66, CY8C20396 Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here: Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE).
PAGE 5
CY8C20x36/46/66, CY8C20396 Development Tools PSoC Designer™ is a Microsoft® Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows XP and Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers.
PAGE 6
CY8C20x36/46/66, CY8C20396 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions.
PAGE 7
CY8C20x36/46/66, CY8C20396 Document Conventions Acronyms Used Units of Measure The following table lists the acronyms that are used in this document. A units of measure table is located in the Electrical Specifications section. Table 9 on page 15 lists all the abbreviations used to measure the PSoC devices. Table 1.
PAGE 8
CY8C20x36/46/66, CY8C20396 Pinouts The CY8C20x36/46/66, CY8C20396 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital IO. 16-Pin QFN Table 2.
PAGE 9
CY8C20x36/46/66, CY8C20396 24-Pin QFN Table 3.
PAGE 10
CY8C20x36/46/66, CY8C20396 24-Pin QFN with USB Pinout Table 4.
PAGE 11
CY8C20x36/46/66, CY8C20396 32-Pin QFN Table 5. Pin Definitions - CY8C20436/46/66 PSoC Device [2, 3] P2[3] Crystal input (XIn) 5 IO I P2[1] 6 IO I P3[3] 7 IO I P3[1] 8 IOHR I P1[7] I2C SCL, SPI SS 9 IOHR I P1[5] I2C SDA, SPI MISO 10 IOHR I P1[3] SPI CLK. 11 IOHR I P1[1] ISSP CLK[1], I2C SCL, SPI MOSI. 12 Vss Ground connection. 13 IOHR Power I P1[0] ISSP DATA[1], I2C SDA.
PAGE 12
CY8C20x36/46/66, CY8C20396 48-Pin QFN Table 6.
PAGE 13
CY8C20x36/46/66, CY8C20396 48-Pin SSOP Figure 7.
PAGE 14
CY8C20x36/46/66, CY8C20396 48-Pin QFN OCD The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit debugging.[4] Table 8.
PAGE 15
CY8C20x36/46/66, CY8C20396 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x36/46/66, CY8C20396 PSoC devices. For the latest electrical specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Figure 9. Voltage versus CPU Frequency Figure 10. IMO Frequency Trim Options 5.5V 5.5V Vdd Voltage Vdd Voltage l id g Va ratin n pe io O Reg 1.
PAGE 16
CY8C20x36/46/66, CY8C20396 Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V. Table 10. Comparator User Module Electrical Specifications Symbol Typ Max Units 70 100 ns Offset 2.
PAGE 17
CY8C20x36/46/66, CY8C20396 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 12. Absolute Maximum Ratings Symbol Description Conditions Min Typ Max Units Higher storage temperatures reduces data retention time. Recommended Storage Temperature is +25°C ± 25°C. Extended duration storage temperatures above 85oC degrades reliability. –55 +25 +125 °C –0.5 – +6.
PAGE 18
CY8C20x36/46/66, CY8C20396 DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and –40°C ≤ TA ≤ 85°C, 2.4V to 3.0V and –40°C ≤ TA ≤ 85°C, or 1.71V to 2.4V and –40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 15. 3.0V to 5.
PAGE 19
CY8C20x36/46/66, CY8C20396 Table 16. 2.4V to 3.0V DC GPIO Specifications Symbol Description Min Typ Max Units 4 5.6 8 kΩ IOH < 10 μA, maximum of 10 mA source current in all IOs Vdd - 0.2 – – V High Output Voltage Port 2 or 3 Pins IOH = 0.2 mA, maximum of 10 mA source current in all IOs Vdd - 0.4 – – V VOH3 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH < 10 μA, maximum of 10 mA source current in all IOs Vdd - 0.
PAGE 20
CY8C20x36/46/66, CY8C20396 Table 17. 1.71V to 2.4V DC GPIO Specifications (continued) Symbol Description Conditions Min Typ Max Units VH Input Hysteresis Voltage – 80 – mV IIL Input Leakage (Absolute Value) – 0.001 1 μA CPIN Capacitive Load on Pins 0.5 1.7 5 pF Package and pin dependent Temp = 25oC Table 18.DC Characteristics – USB Interface Symbol Min Typ Max Units USB D+ Pull Up Resistance With idle bus 0.900 - 1.
PAGE 21
CY8C20x36/46/66, CY8C20396 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 21.
PAGE 22
CY8C20x36/46/66, CY8C20396 AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 23. AC Chip-Level Specifications Symbol Description Conditions Min Typ Max Units FMAX Maximum Operating Frequency 24 – – MHz FCPU Maximum Processing Frequency 24 – – MHz F32K1 Internal Low Speed Oscillator Frequency 19 32 50 kHz FIMO24 Internal Main Oscillator Frequency at 24 MHz Setting 22.8 24 25.
PAGE 23
CY8C20x36/46/66, CY8C20396 Figure 11. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise23 TRise01 TRise23L TRise01L TFall TFallL Table 25.AC Characteristics – USB Data Timings Symbol Tdrate Description Full speed data rate Min Typ Max Units Average bit rate Conditions 12–0.25% 12 12 + 0.25% MHz Tdjr1 Receiver data jitter tolerance To next transition -18.5 – 18.
PAGE 24
CY8C20x36/46/66, CY8C20396 AC External Clock Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 29. AC External Clock Specifications Symbol Description Conditions Min Typ Max Units FOSCEXT Frequency 0.750 – High Period 20.6 – 25.2 MHz – 5300 ns – Low Period – Power Up IMO to Switch 20.6 – – ns 150 – – μs AC Programming Specifications Figure 12.
PAGE 25
CY8C20x36/46/66, CY8C20396 AC SPI Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 31. AC SPI Specifications Symbol FSPIM FSPIS Description Conditions Min Typ Max Units Maximum Input Clock Frequency Selection, Master 2.4V
PAGE 26
CY8C20x36/46/66, CY8C20396 Packaging Information This section illustrates the packaging specifications for the CY8C20x36/46/66, CY8C20396 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 14.
PAGE 27
CY8C20x36/46/66, CY8C20396 Figure 16. 32-Pin (5x5 x 0.6 mm) QFN SEE NOTE 1 TOP VIEW BOTTOM VIEW SIDE VIEW NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED PAD CYPRESS COMPANY CONFIDENTIAL 2. BASED ON REF JEDEC # MO-248 TITLE 3. PACKAGE WEIGHT: 0.0388g 4. DIMENSIONS ARE IN MILLIMETERS 32L QFN 5 X 5 X 0.55 MM PACKAGE OUTLINE 3.5 X 3.5 EPAD (SAWN TYPE) SIZE PART NO. A LQ32 001-42168 *C REV DWG NO 001-42168 *C Figure 17. 48-Pin (300 MIL) SSOP .020 24 1 0.395 0.420 0.292 0.
PAGE 28
CY8C20x36/46/66, CY8C20396 Figure 18. 48-Pin (7x7 mm) QFN 001-13191 *C Important Notes ■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. ■ Pinned vias for thermal conduction are not required for the low power PSoC device. Thermal Impedances Table 33. Thermal Impedances per Package Package Typical θJA [11] 16 QFN 32.69oC/W 24 QFN[12] 20.90oC/W 32 QFN[12] 19.
PAGE 29
CY8C20x36/46/66, CY8C20396 Development Tool Selection Software Development Kits PSoC Designer™ All development kits are sold at the Cypress Online Store. At the core of the PSoC development software suite is PSoC Designer. This is used by thousands of PSoC developers. This robust software is facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers.
PAGE 30
CY8C20x36/46/66, CY8C20396 Evaluation Tools Device Programmers All evaluation tools are sold at the Cypress Online Store. All device programmers are purchased from the Cypress Online Store. CY3210-MiniProg1 CY3216 Modular Programmer The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable.
PAGE 31
CY8C20x36/46/66, CY8C20396 Accessories (Emulation and Programming) Table 35.
PAGE 32
CY8C20x36/46/66, CY8C20396 Ordering Information The following table lists the CY8C20x36/46/66, CY8C20396 PSoC devices key package features and ordering codes. Table 36. PSoC Device Key Features and Ordering Information Package Ordering Code Flash SRAM CapSense (Bytes) (Bytes) Blocks Digital IO Analog XRES Pins Inputs Pin USB 16-Pin (3x3x0.6mm) QFN CY8C20236-24LKXI 8K 1K 1 13 13 Yes No 16-Pin (3x3x0.6mm) QFN (Tape and Reel) CY8C20236-24LKXIT 8K 1K 1 13 13 Yes No 24-Pin (4x4x0.
PAGE 33
CY8C20x36/46/66, CY8C20396 Document History Page Document Title: CY8C20x36/46/66, CY8C20396 CapSenseTM Applications Document Number: 001-12696 Revision ECN Origin of Change Submission Date Description of Change ** 766857 HMT See ECN New silicon and document (Revision **). *A 1242866 HMT See ECN Add features. Update all applicable sections. Update specs. Fix 24-pin QFN pinout moving pins inside. Update package revisions. Update and add to Emulation and Programming Accessories table.
PAGE 34
CY8C20x36/46/66, CY8C20396 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.