Specifications

106 CY8CKIT-042 PSoC 4 Pioneer Kit Guide, Doc. # 001-86371 Rev. *D
A.2.3 PSoC 5LP GPIO Header (J8)
J8 is a 2×6 header that connects PSoC 5LP pins to support GPIO controls for custom PSoC 5LP projects.
A.3 Program and Debug Headers
A.3.1 PSoC 4 Direct Program/Debug Header (J6)
A.3.2 PSoC 5LP Direct Program/Debug Header (J7)
J8
Pin PSoC 5LP Signal PSoC 5LP Description Pin
PSoC 5LP
Signal
PSoC 5LP Description
J8_01 PSoC 5LP_VDD VDD J8_02 P1[2] Digital I/O
J8_03 P0[0] Delta Sigma ADC + input J8_04 P0[1] Delta Sigma ADC – input
J8_05 P3[4] SAR – input J8_06 P3[5] SAR + input
J8_07 P3[6] Buffered VDAC J8_08 P3[7] Buffered VDAC
J8_09 P12[6] UART RX J8_10 P12[7] UART TX
J8_11 GND GND J8_12 P3[0] IDAC output
J6
Pin
PSoC 5LP
Signal
PSoC 4
Signal
Description Pin
PSoC 5LP
Signal
PSoC 4
Signal
Description
J6_01 VDD VDD VCC J6_02 P2[0] P3[2] TMS/SWDIO
J6_03 GND GND GND J6_04 P2[1] P3[3] TCLK/SWCLK
J6_05 GND GND GND J6_06 P2[2] NC TDO/SWO
J6_07 NC GND GND J6_08 P2[3] NC TDI
J6_09 GND GND GND J6_10 P2[4] XRES RESET
J7
Pin
PSoC 5LP
Signal
Description Pin
PSoC 5LP
Signal
Description
J7_01 VDD VCC J7_02 P1[0] TMS/SWDIO
J7_03 GND GND J7_04 P1[1] TCLK/SWCLK
J7_05 GND GND J7_06 P1[3] TDO/SWO
J7_07 GND GND J7_08 P1[4] TDI
J7_09 GND GND J7_10 XRES RESET