Specifications

30 CY8CKIT-042 PSoC 4 Pioneer Kit Guide, Doc. # 001-86371 Rev. *D
Hardware
4.3 Functional Description
4.3.1 PSoC 4
This kit uses the PSoC 4200 family device. PSoC 4200 devices are a combination of a
microcontroller with programmable logic, high-performance analog-to-digital conversion, two
opamps with comparator mode, and commonly used fixed-function peripherals. For more
information, refer to the PSoC 4 web page and the PSoC 4200 family datasheet.
Features
■ 32-bit MCU subsystem
❐ 48 MHz ARM Cortex-M0 CPU with single cycle multiply
❐ Up to 32 KB of flash with read accelerator
❐ Up to 4 KB of SRAM
■ Programmable analog
❐ Two opamps with reconfigurable high-drive external and high-bandwidth internal drive, com-
parator modes, and ADC input buffering capability
❐ 12-bit 1-Msps SAR ADC with differential and single-ended modes; channel sequencer with
signal averaging
❐ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
❐ Two low-power comparators that operate in deep sleep
■ Programmable digital
❐ Four programmable logic blocks called universal digital blocks (UDBs), each with eight Macro-
cells and data path
❐ Cypress-provided peripheral component library, user-defined state machines, and Verilog
input
■ Low power 1.71 to 5.5 V operation
❐ 20-nA Stop mode with GPIO pin wakeup
❐ Hibernate and Deep-Sleep modes allow wakeup-time versus power trade-offs
■ Capacitive sensing
❐ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (greater than 5:1) and
water tolerance
❐ Cypress-supplied software component makes capacitive sensing design easy
❐ Automatic hardware tuning (SmartSense™)
■ Segment LCD drive
❐ LCD drive supported on all pins (common or segment)
❐ Operates in Deep-Sleep mode with 4 bits per pin memory
■ Serial communication
❐ Two independent run-time reconfigurable serial communication blocks (SCBs) with re-config-
urable I2C, SPI, or UART functionality
■ Timing and pulse-width modulation
❐ Four 16-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks
❐ Center-aligned, Edge, and Pseudo-random modes
❐ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital
logic applications
■ Up to 36 programmable GPIOs
❐ 44-pin TQFP, 40-pin QFN, and 28-pin SSOP packages
❐ Any GPIO pin can be Capsense, LCD, analog, or digital
❐ Drive modes, strengths, and slew rates are programmable
■ PSoC Creator design environment
❐ Integrated development environment (IDE) provides schematic design entry and build (with
analog and digital automatic routing)