Specifications

CY8CKIT-042 PSoC 4 Pioneer Kit Guide, Doc. # 001-86371 Rev. *D 31
Hardware
Applications Programming Interface (API) component for all fixed-function and programmable
peripherals
Industry-standard tool compatibility
After schematic entry, development can be done with ARM-based industry-standard develop-
ment tools
For more information see the CY8C42 family datasheet.
4.3.2 PSoC 5LP
An onboard PSoC 5LP is used to program and debug PSoC 4. The PSoC 5LP connects to the USB
port of the PC through a USB Mini B connector and to the SWD interface of the PSoC 4 device.
PSoC 5LP is a true system-level solution providing MCU, memory, analog, and digital peripheral
functions in a single chip. The CY8C58LPxx family offers a modern method of signal acquisition,
signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog
capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. For more
information, refer to the PSoC 5LP web page.
Features
32-bit ARM Cortex-M3 CPU core
DC to 67-MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention, and multiple
security features
Up to 32-KB flash error correcting code (ECC) or configuration storage
Up to 64 KB SRAM
2-KB electrically erasable programmable read-only memory (EEPROM) memory, 1 M cycles,
and 20 years retention
24-channel direct memory access (DMA) with multilayer AHB bus access
a.Programmable chained descriptors and priorities
b.High bandwidth 32-bit transfer support
Low voltage, ultra low power
Wide operating voltage range: 0.5 V to 5.5 V
High-efficiency boost regulator from 0.5 V input to 1.8 V to 5.0 V output
3.1 mA at 6 MHz
Low power modes including:
a.2-µA sleep mode with real time clock (RTC) and low-voltage detect (LVD) interrupt
b.300-nA hibernate mode with RAM retention
Versatile I/O system
28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs)
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46×16 segments
CapSense support from any GPIO[3]
1.2 V to 5.5 V I/O interface voltages, up to 4 domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIOs configurable as open drain high/low, pull-up/pull-down, High-Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
20 to 24 programmable logic device (PLD) based universal digital blocks (UDBs)
Full CAN 2.0b 16 RX, 8 TX buffers
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator