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ADVANCE

CY14B108L, CY14B108N

8-Mbit (1024K x 8/512K x 16) nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-45523 Rev. *A Revised June 24, 2008

Features

■ 20 ns, 25 ns, and 45 ns access times

■ Internally organized as 1024K x 8 (CY14B108L) or 512K x 16

(CY14B108N)

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap

nonvolatile elements initiated by

software, device pin, or AutoStore

on power down

■ RECALL to SRAM initiated by software or power up

■ Infinite read, write, and recall cycles

■ 200,000 STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 3V +20%, –10% operation

■ Commercial and industrial temperatures

■ 48-pin FBGA, 44 and 54-pin TSOP II packages

■ Pb-free and RoHS compliance

Functional Description

The Cypress CY14B108L/CY14B108N is a fast static RAM, with

a nonvolatile element in each memory cell. The memory is

organized as 1024K words of 8 bits each or 512K words of 16

bits each. The embedded nonvolatile elements incorporate

QuantumTrap technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while independent nonvolatile data resides in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile memory.

Both the STORE and RECALL operations are also available

under software control.

- A

Address

CAP

DQ0 - DQ7

HSB

CY14B108L

BHE

BLE

Logic Block Diagram

[1]

CY14B108N

Note

1. Address A

- A

and Data DQ0 - DQ7 for x8 configuration, Address A

- A

and Data DQ0 - DQ15 for x16 configuration.

[+] Feedback

Summary of content (20 pages)

PAGE 1
ADVANCE CY14B108L, CY14B108N 8-Mbit (1024K x 8/512K x 16) nvSRAM Features Functional Description ■ 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 1024K x 8 (CY14B108L) or 512K x 16 (CY14B108N) ■ Hands off automatic STORE on power down with only a small capacitor ■ STORE to QuantumTrap® nonvolatile elements initiated by software, device pin, or AutoStore® on power down ■ RECALL to SRAM initiated by software or power up ■ Infinite read, write, and recall cycles ■ 200,000 STORE
PAGE 2
ADVANCE CY14B108L, CY14B108N Pinouts Figure 1.
PAGE 3
ADVANCE CY14B108L, CY14B108N Pin Definitions Pin Name IO Type Description A0 – A19 Input Address Inputs Used to Select One of the 1,048,576 bytes of the nvSRAM for x8 Configuration. A0 – A18 DQ0 – DQ7 Address Inputs Used to Select One of the 524, 288 bytes of the nvSRAM for x16 Configuration. Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on operation. Bidirectional Data IO Lines for x16 Configuration.
PAGE 4
ADVANCE CY14B108L, CY14B108N The CY14B108L/CY14B108N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture all cells are stored and recalled in parallel.
PAGE 5
ADVANCE CY14B108L, CY14B108N Software STORE is disabled. It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the READ and WRITE operation. Transfer data from the SRAM to the nonvolatile memory with a software address sequence.
PAGE 6
ADVANCE CY14B108L, CY14B108N Table 1.
PAGE 7
ADVANCE CY14B108L, CY14B108N Maximum Ratings Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260°C Storage Temperature ................................. –65°C to +150°C Output Short Circuit Current [6] ....................................
PAGE 8
ADVANCE CY14B108L, CY14B108N Capacitance In the following table, the capacitance parameters are listed[9]. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0V Max Unit 14 pF 14 pF Thermal Resistance In the following table, the thermal resistance parameters are listed[9].
PAGE 9
ADVANCE CY14B108L, CY14B108N AC Switching Characteristics In the following table, the AC switching characteristics are listed.
PAGE 10
ADVANCE CY14B108L, CY14B108N AutoStore or Power Up RECALL Parameters CY14B108L/CY14B108N Description Min Unit Max tHRECALL [14] Power Up RECALL Duration 20 ms tSTORE [15] STORE Cycle Duration 15 ms VSWITCH Low Voltage Trigger Level tVCCRISE VCC Rise Time 2.65 V μs 150 Software Controlled STORE/RECALL Cycle In the following table, the software controlled STORE/RECALL cycle parameters are listed[16, 17].
PAGE 11
ADVANCE CY14B108L, CY14B108N Switching Waveforms (continued) Figure 6. SRAM Read Cycle #2: CE and OE Controlled[10, 21, 23] tRC ADDRESS tACE tLZCE CE tPD tHZCE OE tLZOE t HZOE tDOE BHE , BLE tLZBE DQ (DATA OUT) tHZCE tHZBE tDBE DATA VALID t PU ACTIVE STANDBY ICC Figure 7. SRAM Write Cycle #1: WE Controlled[13, 21, 22, 23] t WC ADDRESS t HA t SCE CE t AW t SA t PWE WE t BW BHE , BLE t SD DATA VALID DATA IN tHZWE DATA OUT t HD PREVIOUS DATA HIGH IMPEDANCE t LZWE Notes 22.
PAGE 12
ADVANCE CY14B108L, CY14B108N Switching Waveforms (continued) Figure 8. SRAM Write Cycle #2: CE Controlled[13, 21, 22, 23] tWC ADDRESS tSA tSCE CE tHA tAW tPWE WE tBW BHE , BLE tSD DATA IN tHD DATA VALID HIGH IMPEDANCE DATA OUT Figure 9. AutoStore or Power Up RECALL[24] No STORE occurs without atleast one SRAM write STORE occurs only if a SRAM write has happened VCC VSWITCH tVCCRISE AutoStore tSTORE tSTORE POWER-UP RECALL tHRECALL tHRECALL Read & Write Inhibited Note 24.
PAGE 13
ADVANCE CY14B108L, CY14B108N Switching Waveforms (continued) Figure 10. CE Controlled Software STORE/RECALL Cycle[17] Figure 11. OE Controlled Software STORE/RECALL Cycle[17] tRC ADDRESS # 1 ADDRESS CE tAS ADDRESS # 6 tCW OE tGHAX DATA VALID Document Number: 001-45523 Rev.
PAGE 14
ADVANCE CY14B108L, CY14B108N Switching Waveforms (continued) Figure 12. Hardware STORE Cycle[20] Figure 13. Soft Sequence Processing[18, 19] tSS Document Number: 001-45523 Rev.
PAGE 15
ADVANCE CY14B108L, CY14B108N Ordering Information Speed (ns) 20 25 Ordering Code Package Diagram Package Type Operating Range CY14B108L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B108L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B108L-ZS20XI 51-85087 44-pin TSOP II CY14B108L-BA20XCT 51-85128 48-ball FBGA Commercial CY14B108L-BA20XIT 51-85128 48-ball FBGA Industrial CY14B108L-BA20XI 51-85128 48-ball FBGA CY14B108L-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14B108L-Z
PAGE 16
ADVANCE CY14B108L, CY14B108N Ordering Information (continued) Speed (ns) 45 Ordering Code Package Diagram Operating Range Package Type CY14B108L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B108L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B108L-ZS45XI 51-85087 44-pin TSOP II CY14B108L-BA45XCT 51-85128 48-ball FBGA Commercial Industrial CY14B108L-BA45XIT 51-85128 48-ball FBGA CY14B108L-BA45XI 51-85128 48-ball FBGA CY14B108L-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14
PAGE 17
ADVANCE CY14B108L, CY14B108N Package Diagrams Figure 14. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 1 23 10.262 (0.404) 10.058 (0.396) 11.938 (0.470) 11.735 (0.462) 22 EJECTOR PIN 44 TOP VIEW 0.800 BSC (0.0315) OR E K X A SG BOTTOM VIEW 0.400(0.016) 0.300 (0.012) 10.262 (0.404) 10.058 (0.396) BASE PLANE 0.210 (0.0083) 0.120 (0.0047) 0°-5° 0.10 (.004) Document Number: 001-45523 Rev. *A 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 18.517 (0.
PAGE 18
ADVANCE CY14B108L, CY14B108N Package Diagrams (continued) Figure 15. 48-ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 10.00±0.10 10.00±0.10 1 F G H H 1.875 A A B 0.75 6.00±0.10 0.53±0.05 B 0.15 C 0.21±0.05 0.25 C 3.75 6.00±0.10 0.15(4X) Document Number: 001-45523 Rev. *A 1.20 MAX 0.
PAGE 19
ADVANCE CY14B108L, CY14B108N Package Diagrams (continued) Figure 16. 54-Pin TSOP II (51-85160) 51-85160-** Document Number: 001-45523 Rev.
PAGE 20
ADVANCE CY14B108L, CY14B108N Document History Page Document Title: CY14B108L/CY14B108N 8-Mbit (1024K x 8/512K x 16) nvSRAM Document Number: 001- 45523 REV. ECN NO. Submission Date Orig.