1 Mbit nvSRAM Specification Sheet

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CY14B101L

1 Mbit (128K x 8) nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document Number: 001-06400 Rev. *I Revised January 30, 2009

Features

■

25 ns, 35 ns, and 45 ns access times

■

Pin compatible with STK14CA8

■

Hands off automatic STORE on power down with only a small

capacitor

■

STORE to QuantumTrap™ nonvolatile elements is initiated by

software, hardware, or AutoStore™ on power down

■

RECALL to SRAM initiated by software or power up

■

Unlimited READ, WRITE, and RECALL cycles

■

200,000 STORE cycles to QuantumTrap

■

20 year data retention at 55°C

■

Single 3V +20%, –10% operation

■

Commercial and industrial temperature

■

32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages

■

RoHS compliance

Functional Description

The Cypress CY14B101L is a fast static RAM with a nonvolatile

element in each memory cell. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM provides

unlimited read and write cycles, while independent, nonvolatile

data resides in the highly reliable QuantumTrap cell. Data

transfers from the SRAM to the nonvolatile elements (the

STORE operation) takes place automatically at power down. On

power up, data is restored to the SRAM (the RECALL operation)

from the nonvolatile memory. Both the STORE and RECALL

operations are also available under software control.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

1024 X 1024

QuantumTrap

1024 x 1024

STORE

RECALL

COLUMN IO

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

Logic Block Diagram

[+] Feedback

Summary of content (18 pages)

PAGE 1
CY14B101L 1 Mbit (128K x 8) nvSRAM Features Functional Description ■ 25 ns, 35 ns, and 45 ns access times ■ Pin compatible with STK14CA8 ■ Hands off automatic STORE on power down with only a small capacitor ■ STORE to QuantumTrap™ nonvolatile elements is initiated by software, hardware, or AutoStore™ on power down ■ RECALL to SRAM initiated by software or power up ■ Unlimited READ, WRITE, and RECALL cycles The Cypress CY14B101L is a fast static RAM with a nonvolatile element in each memory c
PAGE 2
CY14B101L Pinouts Figure 1.
PAGE 3
CY14B101L Figure 2. AutoStore Mode V CC V CC 0.1UF V CAP 10k Ohm The CY14B101L nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel.
PAGE 4
CY14B101L Hardware RECALL (Power Up) Data Protection During power up or after any low power condition (VCC < VSWITCH), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. The CY14B101L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC is less than VSWITCH.
PAGE 5
CY14B101L Preventing Store Best Practices Disable the AutoStore function by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, perform the following sequence of CE controlled READ operations: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6.
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CY14B101L . Table 1.
PAGE 7
CY14B101L Maximum Ratings Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Surface Mount Lead Soldering Temperature (3 Seconds) .......................................... +260°C Storage Temperature ................................. –65°C to +150°C DC output Current (1 output at a time, 1s duration) ....
PAGE 8
CY14B101L Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention at 55°C 20 Years NVC Nonvolatile STORE Operations 200 K Max Unit Capacitance In the following table, the capacitance parameters are listed.[6] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0V 7 pF 7 pF Thermal Resistance In the following table, the thermal resistance parameters are listed.
PAGE 9
CY14B101L AC Switching Characteristics SRAM Read Cycle Parameter Cypress Alt Parameter tACE tELQV [7] tAVAV, tELEH tRC tAA [8] tAVQV tDOE tGLQV tAXQX tOHA [8] tLZCE [9] tELQX tHZCE [9] tEHQZ [9] tGLQX tLZOE tHZOE [9] tGHQZ tPU [6] tELICCH tEHICCL tPD [6] 25 ns Description Min Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to O
PAGE 10
CY14B101L SRAM Write Cycle Parameter Cypress Alt Parameter tWC tAVAV tPWE tWLWH, tWLEH tELWH, tELEH tSCE tDVWH, tDVEH tSD tHD tWHDX, tEHDX tAVWH, tAVEH tAW tAVWL, tAVEL tSA tHA tWHAX, tEHAX tWLQZ tHZWE [9,11] tWHQX tLZWE [9] 25 ns Description Min Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active Aft
PAGE 11
CY14B101L AutoStore or Power Up RECALL Parameter Alt tHRECALL [13] tSTORE [14, 15] VSWITCH tVCCRISE CY14B101L Min Max 20 12.5 2.65 150 Description tRESTORE tHLHZ Power up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time Unit ms ms V μs Switching Waveforms Figure 9.
PAGE 12
CY14B101L Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [16, 17] Parameter Alt Description 25 ns Min 35 ns Max Min Max 45 ns Min Max Unit tRC[17] tAVAV STORE/RECALL Initiation Cycle Time 25 35 45 ns tSA tAVEL Address Setup Time 0 0 0 ns tCW tELEH Clock Pulse Width 20 25 30 ns tHA tGHAX, tELAX Address Hold Time 1 1 1 ns RECALL Duration tRECALL 120 120 120 μs Switching Waveforms Figure 10.
PAGE 13
CY14B101L Hardware STORE Cycle Parameter tPHSB tDELAY [18] Alt CY14B101L Description Min tHLHX Hardware STORE Pulse Width 15 tHLQZ , tBLQZ Time Allowed to Complete SRAM Cycle 1 tss[19, 20] Soft Sequence Processing Time Max Unit ns 70 μs 70 us Switching Waveforms Figure 12. Hardware STORE Cycle 3+6% Figure 13. Soft Sequence Processing[19, 20] 6RIW 6HTXHQFH &RPPDQG $GGUHVV $GGUHVV W6$ $GGUHVV W&: W66 6RIW 6HTXHQFH &RPPDQG $GGUHVV W66 $GGUHVV W&: &( 9&& Notes 18.
PAGE 14
CY14B101L Part Numbering Nomenclature CY 14 B 101 L - SZ 25 X C T Option T - Tape and Reel Blank - Std. Temperature C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Pb-Free Speed 25 - 25 ns 35 - 35 ns 45 - 45 ns Package SZ - 32 SOIC SP - 48 SSOP Data Bus L - x8 Density 101 - 1 Mb Voltage B - 3.
PAGE 15
CY14B101L Ordering Information Speed (ns) 45 Ordering Code Package Diagram Operating Range Package Type CY14B101L-SZ45XCT 51-85127 32-pin SOIC CY14B101L-SZ45XC 51-85127 32-pin SOIC CY14B101L-SP45XCT 51-85061 48-pin SSOP CY14B101L-SP45XC 51-85061 48-pin SSOP CY14B101L-SZ45XIT 51-85127 32-pin SOIC CY14B101L-SZ45XI 51-85127 32-pin SOIC CY14B101L-SP45XIT 51-85061 48-pin SSOP CY14B101L-SP45XI 51-85061 48-pin SSOP Commercial Industrial All parts are Pb-free.
PAGE 16
CY14B101L Package Diagrams (continued) Figure 15. 48-Pin Shrunk Small Outline Package (51-85061) 51-85061-*C Document Number: 001-06400 Rev.
PAGE 17
CY14B101L Document History Page Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM Document Number: 001-06400 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 425138 TUP New data sheet *A 437321 TUP Show data sheet on External Web *B 471966 TUP Changed ICC3 from 5 mA to 10 mA Changed ISB from 2 mA to 3 mA Changed VIH(min) from 2.2V to 2.
PAGE 18
CY14B101L Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.