Specifications

STK17TA8
Document #: 001-52039 Rev. *C Page 14 of 24
atile elements. Once a STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Once the sixth address in the sequence has been entered, the
STORE cycle starts and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence
and that G
is active. After the t
STORE
cycle time has been fulfilled,
the SRAM is again activated for READ and WRITE operation.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of E
or G controlled or READ operations
must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is trans-
ferred into the SRAM cells. After the t
RECALL
cycle time, the
SRAM is once again be ready for READ or WRITE operations.
The RECALL operation in no way alters the data in the nonvol-
atile storage elements.
Data Protection
The STK17TA8 protects data from corruption during low-voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low voltage condition is detected when
V
CC
<V
SWITCH
.
If the STK17TA8 is in a WRITE mode (both E
and W low) at
power up, after a RECALL, or after a STORE, the WRITE will be
inhibited until a negative transition on E
or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Noise Considerations
The STK17TA8 is a high speed memory and so must have a high
frequency bypass capacitor of 0.1 µF connected between both
V
CC
pins and V
SS
ground plane with no plane break to chip V
SS
.
Use leads and traces that are as short as possible. As with all
high speed CMOS ICs, careful routing of power, ground, and
signals reduces circuit noise.
Preventing AutoStore
Because of the use of nvSRAM to store critical RTC data, the
AutoStore function cannot be disabled on the STK17TA8.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, should always program a unique NV pattern
(for example, complex 4-byte pattern of 46 E6 49 53 hex or
more random bytes) as part of the final system manufacturing
test to ensure these system routines work consistently.
■ Power up boot firmware routines should rewrite the nvSRAM
into the desired state (autostore enabled and so on). While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, and so on.
■ The OSCEN bit in the Calibration register at 0x1FFF8 should
be set to 1 to preserve battery life when the system is in storage
(see “Stopping And Starting The RTC Oscillator” on page 15).
■ The V
cap
value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the max V
cap
value because the
nvSRAM internal algorithm calculates V
cap
charge time based
on this max Vcap value. Customers that want to use a larger
V
cap
value to make sure there is extra store charge and store
time should discuss their V
cap
size selection with Cypress to
understand any impact on the V
cap
voltage level at the end of
a t
RECALL
period.
Low Average Active Power
CMOS technology provides the STK17TA8 with the benefit of
power supply current that scales with cycle time. Less current is
drawn as the memory cycle time becomes longer than 50 ns.
Figure 15 shows the relationship between I
CC
and
READ/WRITE cycle time. Worst-case current consumption is
shown for commercial temperature range, V
CC
=3.6V, and chip
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn by
the STK17TA8 depends on the following items:
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ration of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
6. I/O loading.
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