Specifications

STK17TA8
Document #: 001-52039 Rev. *C Page 7 of 24
SRAM READ Cycles #1 and #2
Figure 5. SRAM READ Cycle #1: Address Controlled
[4, 5, 7]
Figure 6. SRAM READ Cycle #2: E and G Controlled
[4, 7]
Notes
4. W
must be high during SRAM READ cycles.
5. Device is continuously selected with E
and G both low
6. Measured ± 200mV from steady state output voltage.
7. HSB
must remain high during READ and WRITE cycles.
NO.
Symbols
Parameter
STK17TA8-25
[1]
STK17TA8-45
Units
#1 #2 Alt. Min Max Min Max
1t
ELQV
t
ACS
Chip Enable Access Time 25 45 ns
2t
AVAV
[4]
t
ELEH
[4]
t
RC
Read Cycle Time 25 45 ns
3t
AVQV
[5]
t
AVQV
[5]
t
AA
Address Access Time 25 45 ns
4t
GLQV
t
OE
Output Enable to Data Valid 12 20 ns
5t
AXQX
[5]
t
AXQX
[5]
t
OH
Output Hold after Address Change 3 3 ns
6t
ELQX
t
LZ
Address Change or Chip Enable to Output Active 3 3 ns
7t
EHQZ
[6]
t
HZ
Address Change or Chip Disable to Output
Inactive
10 15 ns
8t
GLQX
t
OLZ
Output Enable to Output Active 0 0 ns
9t
GHQZ
[6]
t
OHZ
Output Disable to Output Inactive 10 15 ns
10 t
ELICCL
[3]
t
PA
Chip Enable to Power Active 0 0 ns
11 t
EHICCH
[3]
t
PS
Chip Disable to Power Standby 25 45 ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
2
29
11
7
9
10
8
4
3
6
1
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