Specifications

STK17TA8
Document #: 001-52039 Rev. *C Page 8 of 24
SRAM WRITE Cycles #1 and #2
Figure 7. SRAM WRITE Cycle #1: W Controlled
[8, 9]
Figure 8. SRAM WRITE Cycle #2: E Controlled
[8, 9]
Notes
8. If W
is low when E goes low, the outputs remain in the high-impedance state.
9.
E or W must be ≥ V
IH
during address transitions.
NO.
Symbols
Parameter
STK17TA8-25
[1]
STK17TA8-45
Units
#1 #2 Alt. Min Max Min Max
11 t
AVAV
t
AVAV
t
WC
Write Cycle Time 25 45 ns
13 t
WLWH
t
WLEH
t
WP
Write Pulse Width 20 30 ns
14 t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write 20 30 ns
15 t
DVWH
t
DVEH
t
DW
Data Setup to End of Write 10 15 ns
16 t
WHDX
t
EHDX
t
DH
Data Hold after End of Write 0 0 ns
17 t
AVWH
t
AVEH
t
AW
Address Setup to End of Write 20 30 ns
18 t
AVWL
t
AVEL
t
AS
Address Setup to Start of Write 0 0 ns
19 t
WHAX
t
EHAX
t
WR
Address Hold after End of Write 0 0 ns
20 t
WLQZ
6, 8
t
WZ
Write Enable to Output Disable 10 15 ns
21 t
WHQX
t
OW
Output Active after End of Write 3 3 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
11
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA IN
11
t
AVAV
16
t
EHDX
13
t
WLEH
19
t
EHAX
18
t
AVEL
17
t
AVEH
DATA VALID
15
t
DVEH
HIGH IMPEDANCE
14
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN
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