Serial SPI nvSRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY14B101P

PRELIMINARY

CY14B101P

1 Mbit (128K x 8) Serial SPI nvSRAM

with Real Time Clock

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 001-44109 Rev. *B Revised February 2, 2009

Features

■

1 Mbit NonVolatile SRAM

❐

Internally organized as 128K x 8

❐

STORE to QuantumTrap

nonvolatile elements initiated

automatically on power down (AutoStore

) or by user using

HSB pin (Hardware Store) or SPI instruction (Software Store)

❐

RECALL to SRAM initiated on power up (Power Up Recall

)

or by SPI Instruction (Software Recall)

❐

Automatic STORE on power down with a small capacitor

■

High Reliability

❐

Infinite Read, Write, and RECALL cycles

❐

200,000 STORE cycles to QuantumTrap

❐

Data Retention: 20 Years

■

Real Time Clock

❐

Full featured Real Time Clock

❐

Watchdog timer

❐

Clock alarm with programmable interrupts

❐

Capacitor or battery backup for RTC

❐

Backup current of 300 nA

■

High Speed Serial Peripheral Interface (SPI)

❐

40 MHz Clock rate - RTC Read at 25 MHz

❐

Supports SPI Modes 0 (0,0) and 3 (1,1)

■

Write Protection

❐

Hardware Protection using Write Protect (WP) Pin

❐

Software Protection using Write Disable Instruction

❐

Software Block Protection for 1/4, 1/2, or entire Array

■

Low Power Consumption

❐

Single 3V +20%, –10% operation

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Average Vcc current of 10 mA at 40 MHz operation

■

Industry Standard Configurations

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Commercial and industrial temperatures

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16-pin SOIC Package

❐

RoHS compliant

Overview

The Cypress CY14B101P combines a 1 Mbit nonvolatile static

RAM with full featured real time clock in a monolithic integrated

circuit with serial SPI interface. The memory is organized as

128K words of 8 bits each. The embedded nonvolatile elements

incorporate the QuantumTrap technology, creating the world’s

most reliable nonvolatile memory. The SRAM provides infinite

read and write cycles, while the QuantumTrap cells provide

highly reliable nonvolatile storage of data. Data transfers from

SRAM to the nonvolatile elements (STORE operation) takes

place automatically at power down. On power up, data is

restored to the SRAM from the nonvolatile memory (RECALL

operation). The STORE and RECALL operations can also be

initiated by the user.

Instruction

Address

Decoder

Data I/O register

Status register

Power Control

STORE/RECALL

Control

Instruction decode

Write protect

Control logic

Quantum Trap

STORE

RECALL

SCK

CAP

HSB

128K X 8

SRAM ARRAY

128K X 8

RTC

Xout

Xin

INT

MUX

A0-A16

D0-D7

HOLD

Logic Block Diagram

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Summary of content (32 pages)

PAGE 1
PRELIMINARY CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock Features ■ ■ 1 Mbit NonVolatile SRAM ❐ Internally organized as 128K x 8 ® ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power down (AutoStore®) or by user using HSB pin (Hardware Store) or SPI instruction (Software Store) ® ❐ RECALL to SRAM initiated on power up (Power Up Recall ) or by SPI Instruction (Software Recall) ❐ Automatic STORE on power down with a small capacitor ■ Write Protection ❐ Hard
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CY14B101P PRELIMINARY Pinouts Figure 1. Pin Diagram - 16-Pin SOIC NC 1 16 VCC VRTCbat 2 15 INT Xout 3 14 VCAP 13 SO 12 SI Top View Xin 4 WP 5 HOLD 6 11 SCK 7 10 CS 8 9 HSB VRTCcap GND not to scale Table 1. Pin Definitions Pin Name I/O Type Description CS Input Chip Select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low power standby mode. SCK Input Serial Clock. Runs at speeds up to a maximum of 25 MHz.
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PRELIMINARY Device Operation CY14B101P is a 1-Mbit nvSRAM memory with integrated RTC and SPI interface. All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capability to handle infinite writes to the memory. The data in SRAM is secured by a STORE sequence that transfers the data in parallel to the nonvolatile Quantum Trap cells. A small capacitor (VCAP) is used to AutoStore the SRAM data in nonvolatile cells when power goes down providing power down data security.
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PRELIMINARY CY14B101P cycle is in progress. The RECALL operation in no way alters the data in the nonvolatile elements. Figure 2. AutoStore Mode Vcc Hardware Recall (Power Up) During power up, when VCC crosses VSWITCH, an automatic RECALL sequence is initiated which transfers the content of nonvolatile memory on to the SRAM. 10kOhm 0.1uF Vcc CS A Power Up Recall cycle takes tFA time to complete and the memory access is disabled during this time.
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PRELIMINARY master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued. The commonly used terms used in SPI protocol are given below: SPI Master The SPI Master device controls the operations on a SPI bus. An SPI bus may have only one master with one or more slave devices.
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CY14B101P PRELIMINARY Figure 3.
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CY14B101P PRELIMINARY SPI Operating Features Active Power and Standby Power Modes Power Up When Chip Select (CS) is LOW, the device is selected, and is in the Active Power mode. The device consumes ICC current, as specified in DC Electrical Characteristics on page 22. When Chip Select (CS) is HIGH, the device is deselected and the device goes into the Standby Power mode if a STORE or RECALL cycle is not in progress.
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CY14B101P PRELIMINARY Status Register tion and read by RDSR instruction. However, only WPEN, BP1 and BP0 bits of the Status Register can be modified by using WRSR instruction. WRSR instruction has no effect on WEN and RDY bits. The default value shipped from the factory for BP1, BP2 and WPEN bits is ‘0’. The status register bits are listed in Table 3. The status register consists of Ready bit (RDY) and data protection bits BP1, BP0, WEN and WPEN.
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CY14B101P PRELIMINARY Figure 7. Write Status Register (WRSR) Instruction Timing CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Data in Opcode SI 0 0 0 0 0 0 0 1 D7 0 0 0 D3 D2 0 MSB Write Protection and Block Protection CY14B101P provides features for both software and hardware write protection using WRDI instruction and WP. Additionally, this device also provides block protection mechanism through BP0 and BP1 pins of the Status Register.
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CY14B101P PRELIMINARY When WP pin is LOW and WPEN is set to “1”, any modifications to status register are disabled. Therefore, the memory is protected by setting the BP0 and BP1 bits and the WP pin inhibits any modification of the status register bits, providing hardware write protection. data (D7-D0) at the specific address is shifted out on the SO line on the falling edge of SCK. Any other data on SI line after the last address bit is ignored.
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CY14B101P PRELIMINARY Figure 11. Burst Mode Read Instruction Timing CS 2 3 4 5 6 7 1 0 2 3 4 5 6 7 Op-Code 0 0 0 0 1 2 3 4 5 6 7 0 0 7 1 2 3 4 5 6 7 17-bit Address 0 1 0 1 0 0 0 0 0 0 ~ ~ SI 20 21 22 23 0 ~ ~ 1 ~ ~ 0 SCK A16 0 MSB A3 A2 A1 A0 LSB Data Byte N SO ~ ~ Data Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB Figure 12.
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CY14B101P PRELIMINARY Figure 14. Read RTC (RDRTC) Instruction Timing CS 0 1 2 3 4 5 6 1 7 0 1 0 0 MSB 2 4 3 5 6 7 0 1 2 3 4 5 6 7 SCK Op-Code 0 SI 0 0 1 0 0 1 0 0 A3 A2 A1 A0 LSB SO D7 D6 D5 D4 D3 D2 D1 D0 MSB WRITE RTC (WRTC) Instruction LSB Data of data. WRTC allows burst mode write operation. When writing more than one registers in burst mode, the address rolls over to 0x00 after the last RTC address (0x0F) is reached.
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CY14B101P PRELIMINARY bit is cleared on the positive edge of CS following the STORE instruction. bit is cleared on the positive edge of CS following the ASENB instruction. Software Recall (RECALL) Figure 19. AutoStore Enable Operation When a RECALL instruction is executed, CY14B101P performs a Software Recall operation. To issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the RECALL opcode on the SI pin following the falling edge of CS.
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CY14B101P PRELIMINARY Real Time Clock Operation nvTIME Operation The CY14B101P offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. The RTC registers occupy a separate address space from nvSRAM and are accessible through Read RTC (RDRTC) and Write RTC (WRTC) instructions on register addresses 0x00 to 0x0F.
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PRELIMINARY The value of OSCF must be reset to ‘0’ when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit “W” (in the Flags register at 0x00) to a “1” to enable writes to the Flag register. Write a “0” to the OSCF bit and then reset the write bit to “0” to disable writes.
PAGE 16
PRELIMINARY . Interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the Flags register is read by the user. This mode is used as an interrupt to a host microcontroller. The control bits are summarized in the following section. Figure 21.
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CY14B101P PRELIMINARY Accessing the Real Time Clock through SPI CY14B101P uses 16 registers for Real Time Clock (RTC). These registers can be read out or written to by accessing all 16 registers in burst mode or accessing each register, one at a time. The RDRTC and WRTC instructions are used to access the RTC. All the RTC registers can be read in burst mode by issuing the RDRTC instruction and and reading all 16 bytes without bringing the CS pin HIGH.
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CY14B101P PRELIMINARY Table 9.
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CY14B101P PRELIMINARY Table 10. Register Map Detail Time Keeping - Years D7 D6 0x0F D5 D4 D3 D2 10s Years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Time Keeping - Months 0x0E D7 D6 D5 D4 0 0 0 10s Month D3 D2 D1 D0 Months Contains the BCD digits of the month.
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CY14B101P PRELIMINARY Table 10. Register Map Detail (continued) WatchDog Timer 0x07 D7 D6 WDS WDW D5 D4 D3 D2 D1 D0 WDT WDS Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. WDW Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5–D0).
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CY14B101P PRELIMINARY Table 10. Register Map Detail (continued) Alarm - Seconds 0x02 D7 D6 M D5 D4 D3 10s Alarm Seconds D2 D1 D0 Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value. M Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value.
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CY14B101P PRELIMINARY Maximum Ratings Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Storage Temperature ................................. –65°C to +150°C Surface Mount Lead Soldering Temperature (3 Seconds) ..................................
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CY14B101P PRELIMINARY Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 20 Years NVC Nonvolatile STORE Operations 200 K Max Unit 6 pF 8 pF 16-SOIC Unit TBD °C/W TBD °C/W Capacitance Parameter[6] Description CIN Input Capacitance COUT Output Pin Capacitance Test Conditions TA = 25°C, f = 1MHz, VCC = 3.
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CY14B101P PRELIMINARY Table 12. RTC Characteristics Parameters IBAK [7] Description RTC Backup Current Test Conditions Min Typ Max Units o Room Temperature (25 C) 300 nA Hot Temperature (85oC) 450 nA V VRTCbat RTC Battery Pin Voltage 1.8 3.0 3.3 VRTCcap RTC Capacitor Pin Voltage 1.5 3.0 3.6 V tOCS RTC Oscillator Time to Start 1 2 sec AC Switching Characteristics Cypress Parameter Alt.
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CY14B101P PRELIMINARY Figure 25. Synchronous Data Timing (Mode 0) tCS CS tCSS tCH tCL tCSH SCK tSD tHD VALID IN SI tCO SO tOH tHZCS HI-Z HI-Z ~ ~ ~ ~ Figure 26. HOLD Timing CS SCK tSH tHH tHH tSH HOLD tHHZ tHLZ SO Document #: 001-44109 Rev.
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CY14B101P PRELIMINARY AutoStore or Power Up RECALL Parameters CY14B101P Description Min tFA [8] Power Up RECALL Duration tSTORE [9] STORE Cycle Duration tDELAY [10] VSWITCH tVCCRISE Time Allowed to Complete SRAM Cycle VHDIS[6] tLZHSB tHHHD Low Voltage Trigger Level VCC Rise Time HSB Output Driver Disable Voltage Max 20 ms 8 ms 25 ns 2.65 1.9 V µs V 5 500 µs ns 150 HSB To Output Active Time HSB High Active Time Unit Switching Waveforms Figure 27.
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CY14B101P PRELIMINARY Software Controlled STORE/RECALL Cycles CY14B101P Parameter Description Unit Min tRECALL tSS [11, 13] Max RECALL Duration 200 µs Soft Sequence Processing Time 100 µs Figure 28. Software STORE Cycle[13] CS 0 1 2 3 4 5 6 7 SCK SI 0 0 1 1 1 1 0 0 tSTORE Hi-Z RWI RDY Figure 29. Software RECALL Cycle[13] CS 0 1 2 3 4 5 6 7 0 1 1 0 0 0 0 0 SCK SI tRECALL RWI Hi-Z RDY Notes 12.
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CY14B101P PRELIMINARY Hardware STORE Cycle CY14B101P Parameter Description Unit Min tDHSB HSB To Output Active Time when write latch not set tPHSB Hardware STORE Pulse Width Max 25 15 ns ns Figure 30. Hardware STORE Cycle[9] Write Latch set ~ ~ tPHSB HSB (IN) tSTORE tDELAY ~ ~ ~ ~ HSB (OUT) tHHHD SO tLZHSB RWI HSB (OUT) tDELAY RWI Document #: 001-44109 Rev.
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CY14B101P PRELIMINARY Ordering Information Ordering Code Package Diagram Package Type CY14B101P-SFXCT 51-85022 16 SOIC CY14B101P-SFXC 51-85022 16 SOIC CY14B101P-SFXIT 51-85022 16 SOIC CY14B101P-SFXI 51-85022 16 SOIC Operating Range Commercial Industrial All the above parts are Pb - free. The above table contains advance information. Contact your local Cypress sales representative for availability of these parts.
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PRELIMINARY CY14B101P Package Diagrams Figure 31. 16-Pin (300 mil) SOIC Package (51-85022) 51-85022 *B Document #: 001-44109 Rev.
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CY14B101P PRELIMINARY Document History Page Document Title: CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock Document Number: 001-44109 REV. ECN NO. Submission Date Orig.
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PRELIMINARY CY14B101P Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.